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Personal profile

Education/Academic qualification

Computer Sciences, PhD, The University of Texas

… → 1999

Computer Science and Technology, ME, Tsinghua University

… → 1994

Computer Science and Technology, BE, Tsinghua University

… → 1992

Fingerprint Fingerprint is based on mining the text of the experts' scientific documents to create an index of weighted terms, which defines the key subjects of each individual researcher.

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Grants 2003 2020

Networks (circuits)
Foundries
Hardware
Costs
Fabrication
Networks (circuits)
Foundries
Hardware
Costs
Fabrication
Electronic equipment
X ray photoelectron spectroscopy
Semiconductor materials
Computer systems
Costs
Hardware
Critical infrastructures
Semiconductor materials
Information technology
Internet

Research Output 1996 2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel

Wei, X., Yan, C., Zhou, H., Zhou, D. & Zeng, X., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 1040-1045 6 p. 8714992. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Capacitance
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Random walk
Program processors
2 Citations (Scopus)

BESAT: Behavioral SAT-based attack on cyclic logic encryption

Shen, Y., Li, Y., Rezaei, A., Kong, S., Dlott, D. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 657-662 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Feedback
Structural analysis
Hardware security

CyCsat-unresolvable cyclic logic encryption using unreachable states

Rezaei, A., Li, Y., Shen, Y., Kong, S. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 394-399 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Foundries
Feedback
Networks (circuits)
Costs

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Chen, Z., Zhou, H. & Gu, J., Jan 16 2019, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., p. 163-170 8 p. 8615684. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Logic circuits
Resource allocation
RRAM

SigAttack: New High-level SAT-based Attack on Logic Encryptions

Shen, Y., Li, Y., Kong, S., Rezaei, A. & Zhou, H., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 940-943 4 p. 8714924. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Encryption
Cryptography
Attack
Logic
Computer hardware