Grants per year
Personal profile
Education/Academic qualification
Computer Sciences, PhD, The University of Texas
… → 1999
Computer Science and Technology, ME, Tsinghua University
… → 1994
Computer Science and Technology, BE, Tsinghua University
… → 1992
Fingerprint Dive into the research topics where Hai Zhou is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 3 Similar Profiles
Clocks
Engineering & Materials Science
Networks (circuits)
Engineering & Materials Science
Crosstalk
Engineering & Materials Science
Wire
Engineering & Materials Science
Sequential circuits
Engineering & Materials Science
Scheduling
Engineering & Materials Science
Costs
Engineering & Materials Science
Flip flop circuits
Engineering & Materials Science
Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Grants 2003 2020
EAGER: PUF-Locked Circuit Obfuscation for Counterfeit and Piracy Prevention
10/1/16 → 3/31/20
Project: Research project
Networks (circuits)
Foundries
Hardware
Costs
Fabrication
REU Supplement for EAGER: PUF-Locked Circuit Obfuscation for Counterfeit and Piracy Prevention.
10/1/16 → 3/31/20
Project: Research project
Networks (circuits)
Foundries
Hardware
Costs
Fabrication
SaTC: STARSS: ICM: Invariant Carrying Machine for Hardware Assurance
10/1/14 → 9/30/19
Project: Research project
Hardware
Critical infrastructures
Semiconductor materials
Information technology
Internet
XPS: FULL: FP: Design and Synthesis of New Energy-efficient Self-healing Computing Electronics with Real-time Configurability
9/1/15 → 8/31/19
Project: Research project
Electronic equipment
X ray photoelectron spectroscopy
Semiconductor materials
Computer systems
Costs
SHF: Small: Collaborative Research: A Systematic Approach to Multicore Parallel CAD
9/1/11 → 8/31/15
Project: Research project
Research Output 1996 2019
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel
Wei, X., Yan, C., Zhou, H., Zhou, D. & Zeng, X., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 1040-1045 6 p. 8714992. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Capacitance
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Random walk
Program processors
A RRAM-based coarse grain reconfigurable array for neural network accelerators
Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Particle accelerators
accelerators
Neural networks
logic
space storage
3
Citations
(Scopus)
BESAT: Behavioral SAT-based attack on cyclic logic encryption
Shen, Y., Li, Y., Rezaei, A., Kong, S., Dlott, D. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 657-662 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Cryptography
Networks (circuits)
Feedback
Structural analysis
Hardware security
CyCsat-unresolvable cyclic logic encryption using unreachable states
Rezaei, A., Li, Y., Shen, Y., Kong, S. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 394-399 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Cryptography
Foundries
Feedback
Networks (circuits)
Costs
Digital compatible synthesis, placement and implementation of mixed-signal time-domain computing
Chen, Z., Zhou, H. & Gu, J., Jun 2 2019, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a67. (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Placement
Time Domain
Synthesis
Computing
Analogue