Computer Science
Experimental Result
100%
Timing Analysis
40%
Clock Skew
31%
Process Variation
30%
Floorplanning
27%
Clock Period
26%
Buffer Insertion
23%
Sequential Circuit
22%
Efficient Algorithm
21%
Heuristic Algorithm
18%
Lagrangian Relaxation
17%
steiner tree
17%
Delay Variation
16%
Tree Construction
14%
Power Consumption
12%
Hardware Security
12%
Optimal Algorithm
12%
High Level Synthesis
12%
Physical Design
12%
Obfuscation
11%
System-on-Chip
11%
Power Optimization
11%
Optimization Technique
11%
Coupling Capacitance
10%
Polynomial Time
10%
Computer Aided Design
10%
Timing Constraint
9%
Internal Structure
9%
Integrated Circuit
9%
Constraint Graph
9%
Global Routing
9%
Timing Optimization
9%
Interconnect Delay
9%
Iterative Algorithm
8%
Monte Carlo Simulation
8%
Model Checking
7%
Integrated Circuit Design
7%
Dynamic Power
7%
Tree Algorithm
7%
Local Minimum
7%
Hardware Design
7%
Optimisation Rate
7%
Optimization Problem
6%
Longest Interconnect
6%
Polynomial Time Algorithm
6%
Dynamic Programming
5%
Memristor
5%
Timing Verification
5%
Integer-Linear Programming
5%
Pipelining
5%
Keyphrases
Retiming
38%
Floorplanning
35%
Process Variation
26%
Logic Encryption
25%
Clock Skew Scheduling
24%
Buffer Insertion
23%
Sequential Circuits
21%
Lagrangian Relaxation
19%
Static Timing Analysis
17%
Clock Period
17%
Gate Sizing
17%
Delay Variation
14%
Network Flow
13%
Heuristic Algorithms
13%
Spanning Graph
12%
Multi-domain
12%
Statistical Timing Analysis
12%
Steiner Tree Construction
12%
Layout Decomposition
11%
Timing Yield
11%
Steiner Tree
11%
Wirelength
10%
Low Power
10%
Timing Analysis
10%
SAT-based Attack
10%
Physical Design
10%
Fixpoint
10%
Obfuscation
10%
Optimal Algorithm
10%
Time Constraints
9%
Power Consumption
9%
High-level Synthesis
9%
Flip-flop
9%
Downscaling
9%
Timer
9%
Global Routing
9%
Coupling Model
9%
Constraint Graph
9%
Min-cost Flow
8%
System-on-chip
8%
Dummy Fill
8%
Electron Beam Lithography
8%
Encryption
8%
Induced Delay
8%
CycSAT
7%
High Performance
7%
Cycle Ratio
7%
Binary Search
7%
Statistical Timing
7%
Time of Arrival
7%
Engineering
Experimental Result
54%
Process Variation
25%
Crosstalk
25%
Interconnects
18%
Clock Period
16%
Lithography
12%
Electric Power Utilization
10%
Integrated Circuit Design
10%
Flip Flop Circuits
10%
Circuit Design
9%
Sequential Circuits
9%
Integrated Circuit
9%
Feature Size
8%
Metrics
7%
Linear Programming
7%
Design Process
7%
Beam Lithography
7%
Performance Degradation
7%
Power Estimation
7%
Polynomial Time
6%
Flow Problem
6%
Chemical Mechanical Polishing
5%
Nodes
5%
Design Space
5%
System-on-Chip
5%
Binary Search
5%
Gaussians
5%
Iterative Algorithm
5%
Lagrangian Relaxation
5%