Computer Science
Buffer Insertion
23%
Clock Period
26%
Clock Skew
31%
Computer Aided Design
10%
Constraint Graph
9%
Coupling Capacitance
10%
Delay Variation
16%
Dynamic Power
7%
Dynamic Programming
5%
Efficient Algorithm
21%
Experimental Result
100%
Floorplanning
27%
Global Routing
9%
Hardware Design
7%
Hardware Security
12%
Heuristic Algorithm
18%
High Level Synthesis
12%
Integer-Linear Programming
5%
Integrated Circuit
9%
Integrated Circuit Design
7%
Interconnect Delay
9%
Internal Structure
9%
Iterative Algorithm
8%
Lagrangian Relaxation
17%
Local Minimum
7%
Longest Interconnect
6%
Memristor
5%
Model Checking
7%
Monte Carlo Simulation
8%
Obfuscation
11%
Optimal Algorithm
12%
Optimisation Rate
7%
Optimization Problem
6%
Optimization Technique
11%
Physical Design
12%
Pipelining
5%
Polynomial Time
10%
Polynomial Time Algorithm
6%
Power Consumption
12%
Power Optimization
11%
Process Variation
30%
Sequential Circuit
22%
steiner tree
17%
System-on-Chip
11%
Timing Analysis
40%
Timing Constraint
9%
Timing Optimization
9%
Timing Verification
5%
Tree Algorithm
7%
Tree Construction
14%
Keyphrases
Binary Search
7%
Buffer Insertion
23%
Clock Period
17%
Clock Skew Scheduling
24%
Constraint Graph
9%
Coupling Model
9%
Cycle Ratio
7%
CycSAT
7%
Delay Variation
14%
Downscaling
9%
Dummy Fill
8%
Electron Beam Lithography
8%
Encryption
8%
Fixpoint
10%
Flip-flop
9%
Floorplanning
35%
Gate Sizing
17%
Global Routing
9%
Heuristic Algorithms
13%
High Performance
7%
High-level Synthesis
9%
Induced Delay
8%
Lagrangian Relaxation
19%
Layout Decomposition
11%
Logic Encryption
25%
Low Power
10%
Min-cost Flow
8%
Multi-domain
12%
Network Flow
13%
Obfuscation
10%
Optimal Algorithm
10%
Physical Design
10%
Power Consumption
9%
Process Variation
26%
Retiming
38%
SAT-based Attack
10%
Sequential Circuits
21%
Spanning Graph
12%
Static Timing Analysis
17%
Statistical Timing
7%
Statistical Timing Analysis
12%
Steiner Tree
11%
Steiner Tree Construction
12%
System-on-chip
8%
Time Constraints
9%
Time of Arrival
7%
Timer
9%
Timing Analysis
10%
Timing Yield
11%
Wirelength
10%
Engineering
Beam Lithography
7%
Binary Search
5%
Chemical Mechanical Polishing
5%
Circuit Design
9%
Clock Period
16%
Crosstalk
25%
Design Process
7%
Design Space
5%
Electric Power Utilization
10%
Experimental Result
54%
Feature Size
8%
Flip Flop Circuits
10%
Flow Problem
6%
Gaussians
5%
Integrated Circuit
9%
Integrated Circuit Design
10%
Interconnects
18%
Iterative Algorithm
5%
Lagrangian Relaxation
5%
Linear Programming
7%
Lithography
12%
Metrics
7%
Nodes
5%
Performance Degradation
7%
Polynomial Time
6%
Power Estimation
7%
Process Variation
25%
Sequential Circuits
9%
System-on-Chip
5%
