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Research Output 1996 2019

2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel

Wei, X., Yan, C., Zhou, H., Zhou, D. & Zeng, X., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 1040-1045 6 p. 8714992. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Capacitance
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Random walk
Program processors

A RRAM-based coarse grain reconfigurable array for neural network accelerators

Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
accelerators
Neural networks
logic
space storage
5 Citations (Scopus)

BESAT: Behavioral SAT-based attack on cyclic logic encryption

Shen, Y., Li, Y., Rezaei, A., Kong, S., Dlott, D. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 657-662 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Feedback
Structural analysis
Hardware security

CellScope: Automatically Specifying and Verifying Cellular Network Protocols

Yu, Y., Li, Y., Hou, K., Chen, Y., Zhou, H. & Yang, J., Aug 19 2019, SIGCOMM 2019 - Proceedings of the 2019 ACM SIGCOMM Conference Posters and Demos, Part of SIGCOMM 2019. Association for Computing Machinery, Inc, p. 21-23 3 p. (SIGCOMM 2019 - Proceedings of the 2019 ACM SIGCOMM Conference Posters and Demos, Part of SIGCOMM 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access
Model checking
Network protocols
1 Citation (Scopus)

CyCsat-unresolvable cyclic logic encryption using unreachable states

Rezaei, A., Li, Y., Shen, Y., Kong, S. & Zhou, H., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 394-399 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Foundries
Feedback
Networks (circuits)
Costs

Digital compatible synthesis, placement and implementation of mixed-signal time-domain computing

Chen, Z., Zhou, H. & Gu, J., Jun 2 2019, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a67. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Placement
Time Domain
Synthesis
Computing
Analogue
1 Citation (Scopus)

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Chen, Z., Zhou, H. & Gu, J., Jan 16 2019, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., p. 163-170 8 p. 8615684. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Logic circuits
Resource allocation
RRAM

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction

Chen, Z., Zhou, H. & Gu, J., Nov 2019, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 11, p. 2655-2667 13 p., 8782148.

Research output: Contribution to journalArticle

Particle accelerators
RRAM
Experiments

Resolving the trilemma in logic encryption

Zhou, H., Rezaei, A. & Shen, Y., Nov 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 8942076. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Structural analysis
Hardware

SigAttack: New High-level SAT-based Attack on Logic Encryptions

Shen, Y., Li, Y., Kong, S., Rezaei, A. & Zhou, H., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 940-943 4 p. 8714924. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Encryption
Cryptography
Attack
Logic
Computer hardware
2018
7 Citations (Scopus)

A comparative investigation of approximate attacks on logic encryptions

Shen, Y., Rezaei, A. & Zhou, H., Feb 20 2018, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 271-276 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Computer hardware
Sampling
Networks (circuits)

A novel N-retry transactional memory model for multi-thread programming

Lu, K., Yan, C., Zhou, H., Zhou, D. & Zeng, X., May 25 2018, Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Martinez, G., Hill, R., Fox, G., Mueller, P. & Wang, G. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 814-821 8 p. (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multi-thread
Transactional Memory
Memory Model
Computer programming
Transactions

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization

Zhang, Y., Lyu, W., Luk, W. S., Yang, F., Zhou, H., Zhou, D., Pan, D. Z. & Zeng, X., Sep 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 9, p. 1613-1626 14 p., 8360950.

Research output: Contribution to journalArticle

Wire
Linear programming
Lithography
10 Citations (Scopus)

Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks

Rezaei, A., Shen, Y., Kong, S., Gu, J. & Zhou, H., Apr 19 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., p. 85-90 6 p. (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Foundries
Networks (circuits)
Combinatorial circuits
Semiconductor materials
1 Citation (Scopus)

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design

Kong, S., Zhou, H. & Gu, J., Dec 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 12, p. 2648-2660 13 p., 8368092.

Research output: Contribution to journalArticle

Networks (circuits)
Tuning
Memristors
Flip flop circuits
VLSI circuits

Multiobjectivism in Dark Silicon Age

Rezaei, A., Daneshtalab, M. & Zhou, H., Jan 1 2018, Advances in Computers. Hurson, A. R. & Sarbazi-Azad, H. (eds.). Academic Press Inc, p. 83-126 44 p. (Advances in Computers; vol. 110).

Research output: Chapter in Book/Report/Conference proceedingChapter

Silicon
Routers
Embedded systems
Telecommunication links
Scalability
7 Citations (Scopus)

SAT-based bit-flipping attack on logic encryptions

Shen, Y., Rezaei, A. & Zhou, H., Apr 19 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., p. 629-632 4 p. (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Attack
Encryption
Logic
2017
3 Citations (Scopus)

An effective layout decomposition method for dsa with multiple patterning in contact-hole generation

Yang, Y., Luk, W. S., Zhou, H., Pan, D. Z., Zhou, D., Yan, C. & Zeng, X., Sep 1 2017, In : ACM Transactions on Design Automation of Electronic Systems. 23, 1, 11.

Research output: Contribution to journalArticle

Self assembly
Decomposition
Coloring
Lithography
Masks

An efficient algorithm for stencil planning and optimization in E-Beam lithography

Ge, J., Yan, C., Zhou, H., Zhou, D. & Zeng, X., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 366-371 6 p. 7858350. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lithography
Planning
Bins
Throughput
32 Citations (Scopus)

CycSAT: SAT-based attack on cyclic logic encryptions

Zhou, H., Jiang, R. & Kong, S., Dec 13 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., p. 49-56 8 p. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2017-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Feedback
Networks (circuits)
38 Citations (Scopus)

Double DIP: Re-evaluating security of logic encryption algorithms

Shen, Y. & Zhou, H., May 10 2017, GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017. Association for Computing Machinery, p. 179-184 6 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; vol. Part F127756).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Combinatorial circuits
1 Citation (Scopus)

Memristor-Based Clock Design and Optimization with In-Situ Tunability

Kong, S., Gu, J. & Zhou, H., Jul 20 2017, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Reis, R., Stan, M., Huebner, M. & Voros, N. (eds.). IEEE Computer Society, p. 427-432 6 p. 7987557. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Clocks
Tuning
Scheduling
Detectors
11 Citations (Scopus)

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age

Rezaei, A., Zhao, D., Daneshtalab, M. & Zhou, H., Apr 26 2017, Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017. Institute of Electrical and Electronics Engineers Inc., p. 589-592 4 p. 7912708. (Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wireless networks
Silicon
Routers
Temperature control
Telecommunication links
2 Citations (Scopus)

Network flow based cut redistribution and insertion for advanced 1D layout design

Zhang, Y., Luk, W. S., Yang, F., Yan, C., Zhou, H., Zhou, D. & Zeng, X., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 360-365 6 p. 7858349. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inductive logic programming (ILP)
Lithography
Printing
Wire

Structural Transformation-Based Obfuscation

Zhou, H., 2017, Hardware Protection through Obfuscation. Springer International Publishing, p. 221-239 19 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Open Access

Using security invariant to verify confidentiality in hardware design

Kong, S., Shen, Y. & Zhou, H., May 10 2017, GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017. Association for Computing Machinery, p. 487-490 4 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; vol. Part F127756).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Computer hardware description languages
Outsourcing
Model checking
2016
9 Citations (Scopus)

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Yang, Y., Luk, W. S., Pan, D. Z., Zhou, H., Yan, C., Zhou, D. & Zeng, X., Sep 2016, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 9, p. 1532-1545 14 p., 7368163.

Research output: Contribution to journalArticle

Electron beam lithography
Lithography
Decomposition
Masks
Throughput
2015
7 Citations (Scopus)

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography

Yang, Y., Luk, W. S., Zhou, H., Yan, C., Zeng, X. & Zhou, D., Mar 11 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 652-657 6 p. 7059082. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

E-beam Lithography
Patterning
Electron Beam
Lithography
Layout
2 Citations (Scopus)

Layout decomposition with pairwise coloring and adaptive multi-start for triple patterning lithography

Zhang, Y., Luk, W. S., Yang, Y., Zhou, H., Yan, C., Pan, D. Z. & Zeng, X., Nov 2015, In : ACM Transactions on Design Automation of Electronic Systems. 21, 1, 2.

Research output: Contribution to journalArticle

Coloring
Lithography
Decomposition
Color

Multi-parameter clock skew scheduling

Zhou, X., Luk, W. S., Zhou, H., Yang, F., Yan, C. & Zeng, X., Jan 1 2015, In : Integration, the VLSI Journal. 48, 1, p. 129-137 9 p.

Research output: Contribution to journalArticle

Clocks
Scheduling
Convex optimization
Linear programming
Networks (circuits)
11 Citations (Scopus)

On error modeling and analysis of approximate adders

Li, L. & Zhou, H., Jan 1 2015, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2015-January, January, p. 511-518 8 p., 7001399.

Research output: Contribution to journalConference article

Adders
Costs

Synthesis of resilient circuits from guarded atomic actions

Chen, Y. & Zhou, H., Jan 1 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 550-555 6 p. 7059064

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Synthesis
Networks (circuits)
Nondeterminism
Transient Faults
Resiliency
2014

Efficient statistical timing analysis for circuits with post-silicon tunable buffers

Zhou, X., Yang, F., Zhou, H., Gong, M., Zhu, H., Zhang, Y. & Zeng, X., Nov 1 2014, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 11, p. 2227-2235 9 p.

Research output: Contribution to journalArticle

Timing Analysis
Statistical Analysis
Buffer
Silicon
Clocks

On Error Modeling and Analysis of Approximate Adders

Li, L. & Zhou, H., 2014, Proceedings of the Institute of Electrical and Electronics Engineers (IEEE) and Association for Computer Machinery International Conference on Computer-Aided Design (IEEE/ACM ICCAD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Optimal and efficient algorithms for multidomain clock skew scheduling

Li, L., Lu, Y. & Zhou, H., Sep 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 9, p. 1888-1897 10 p., 6607242.

Research output: Contribution to journalArticle

Clocks
Scheduling
Sequential circuits

Recovery-based resilient latency-insensitive systems

Chen, Y., Zeng, X. & Zhou, H., Jan 1 2014, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800317. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Recovery
Networks (circuits)
Clocks
Throughput
Hardware
2013
3 Citations (Scopus)

An efficient method for gradient-aware dummy fill synthesis

Wu, P., Zhou, H., Yan, C., Tao, J. & Zeng, X., Jun 1 2013, In : Integration, the VLSI Journal. 46, 3, p. 301-309 9 p.

Research output: Contribution to journalArticle

Linear programming
Fabrication
12 Citations (Scopus)

Large-scale energy storage system design and optimization for emerging electric-drive vehicles

Wu, J., Wang, J., Li, K., Zhou, H., Lv, Q., Shang, L. & Sun, Y., Mar 11 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 3, p. 325-338 14 p., 6461989.

Research output: Contribution to journalArticle

Electric drives
Energy storage
Systems analysis
Frequency domain analysis
Environmental impact
39 Citations (Scopus)

Layout decomposition with pairwise coloring for multiple patterning lithography

Zhang, Y., Luk, W. S., Zhou, H., Yan, C. & Zeng, X., Dec 1 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers. p. 170-177 8 p. 6691115

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Lithography
Decomposition
Color

Post-routing layer assignment for double patterning with timing critical paths consideration

Sun, J., Lu, Y., Zhou, H., Yan, C. & Zeng, X., Mar 1 2013, In : Integration, the VLSI Journal. 46, 2, p. 153-164 12 p.

Research output: Contribution to journalArticle

Wire
Benchmarking
Lithography
Masks
Capacitance
2 Citations (Scopus)

Resource-constrained high-level datapath optimization in ASIP design

Chen, Y. & Zhou, H., Oct 21 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 198-201 4 p. 6513500. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic programming
Heuristic algorithms
2 Citations (Scopus)

Retiming for soft error minimization under error-latching window constraints

Lu, Y. & Zhou, H., Oct 21 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1008-1013 6 p. 6513656. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
Networks (circuits)
Observability
Integrated circuits

SmipRef: An efficient method for multi-domain clock skew scheduling

Zhi, Y., Luk, W. S., Zhou, H. & Zeng, X., Sep 1 2013, In : Integration, the VLSI Journal. 46, 4, p. 392-403 12 p.

Research output: Contribution to journalArticle

Clocks
Scheduling
Sequential circuits
Flip flop circuits
Linear programming
22 Citations (Scopus)

Structural transformation for best-possible obfuscation of sequential circuits

Li, L. & Zhou, H., Sep 16 2013, Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013. p. 55-60 6 p. 6581566. (Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
Intellectual property
2012
21 Citations (Scopus)

An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Li, L., Kang, P., Lu, Y. & Zhou, H., Dec 1 2012, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. p. 226-232 7 p., 6386613.

Research output: Contribution to journalConference article

Clocks
Costs
Experiments
9 Citations (Scopus)

Buffer minimization in pipelined SDF scheduling on multi-core platforms

Chen, Y. & Zhou, H., Apr 26 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 127-132 6 p. 6164932

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Heuristic algorithms
Data flow graphs
Pipelines
Throughput
13 Citations (Scopus)

Clock skew scheduling for timing speculation

Ye, R., Yuan, F., Zhou, H. & Xu, Q., May 24 2012, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. p. 929-934 6 p. 6176630

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Scheduling
Networks (circuits)
Scheduling algorithms
Industry
3 Citations (Scopus)

Efficient design space exploration for component-based system design

Lu, Y. & Zhou, H., Dec 1 2012, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. p. 466-472 7 p., 6386708.

Research output: Contribution to journalConference article

Systems analysis
Large scale systems
Costs
Transistors
Sampling
1 Citation (Scopus)

Optimal prescribed-domain clock skew scheduling

Li, L., Lu, Y. & Zhou, H., Apr 26 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 523-527 5 p. 6165008. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Scheduling
Scheduling algorithms
Hardness
Networks (circuits)
2011
4 Citations (Scopus)

An efficient algorithm for multi-domain clock skew scheduling

Zhi, Y., Luk, W. S., Zhou, H., Yan, C., Zhu, H. & Zeng, X., May 31 2011, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. p. 1364-1369 6 p. 5763220

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Scheduling
Linear programming
Sequential circuits
Flip flop circuits