If you made any changes in Pure, your changes will be visible here soon.

Research Output 1996 2019

Filter
Article
2019

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction

Chen, Z., Zhou, H. & Gu, J., Nov 2019, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 11, p. 2655-2667 13 p., 8782148.

Research output: Contribution to journalArticle

Particle accelerators
RRAM
Experiments
2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization

Zhang, Y., Lyu, W., Luk, W. S., Yang, F., Zhou, H., Zhou, D., Pan, D. Z. & Zeng, X., Sep 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 9, p. 1613-1626 14 p., 8360950.

Research output: Contribution to journalArticle

Wire
Linear programming
Lithography
1 Citation (Scopus)

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design

Kong, S., Zhou, H. & Gu, J., Dec 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 12, p. 2648-2660 13 p., 8368092.

Research output: Contribution to journalArticle

Networks (circuits)
Tuning
Memristors
Flip flop circuits
VLSI circuits
2017
3 Citations (Scopus)

An effective layout decomposition method for dsa with multiple patterning in contact-hole generation

Yang, Y., Luk, W. S., Zhou, H., Pan, D. Z., Zhou, D., Yan, C. & Zeng, X., Sep 1 2017, In : ACM Transactions on Design Automation of Electronic Systems. 23, 1, 11.

Research output: Contribution to journalArticle

Self assembly
Decomposition
Coloring
Lithography
Masks
2016
9 Citations (Scopus)

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Yang, Y., Luk, W. S., Pan, D. Z., Zhou, H., Yan, C., Zhou, D. & Zeng, X., Sep 2016, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 9, p. 1532-1545 14 p., 7368163.

Research output: Contribution to journalArticle

Electron beam lithography
Lithography
Decomposition
Masks
Throughput
2015
2 Citations (Scopus)

Layout decomposition with pairwise coloring and adaptive multi-start for triple patterning lithography

Zhang, Y., Luk, W. S., Yang, Y., Zhou, H., Yan, C., Pan, D. Z. & Zeng, X., Nov 2015, In : ACM Transactions on Design Automation of Electronic Systems. 21, 1, 2.

Research output: Contribution to journalArticle

Coloring
Lithography
Decomposition
Color

Multi-parameter clock skew scheduling

Zhou, X., Luk, W. S., Zhou, H., Yang, F., Yan, C. & Zeng, X., Jan 1 2015, In : Integration, the VLSI Journal. 48, 1, p. 129-137 9 p.

Research output: Contribution to journalArticle

Clocks
Scheduling
Convex optimization
Linear programming
Networks (circuits)
2014

Efficient statistical timing analysis for circuits with post-silicon tunable buffers

Zhou, X., Yang, F., Zhou, H., Gong, M., Zhu, H., Zhang, Y. & Zeng, X., Nov 1 2014, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 11, p. 2227-2235 9 p.

Research output: Contribution to journalArticle

Timing Analysis
Statistical Analysis
Buffer
Silicon
Clocks
2 Citations (Scopus)

Optimal and efficient algorithms for multidomain clock skew scheduling

Li, L., Lu, Y. & Zhou, H., Sep 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 9, p. 1888-1897 10 p., 6607242.

Research output: Contribution to journalArticle

Clocks
Scheduling
Sequential circuits
2013
3 Citations (Scopus)

An efficient method for gradient-aware dummy fill synthesis

Wu, P., Zhou, H., Yan, C., Tao, J. & Zeng, X., Jun 1 2013, In : Integration, the VLSI Journal. 46, 3, p. 301-309 9 p.

Research output: Contribution to journalArticle

Linear programming
Fabrication
12 Citations (Scopus)

Large-scale energy storage system design and optimization for emerging electric-drive vehicles

Wu, J., Wang, J., Li, K., Zhou, H., Lv, Q., Shang, L. & Sun, Y., Mar 11 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 3, p. 325-338 14 p., 6461989.

Research output: Contribution to journalArticle

Electric drives
Energy storage
Systems analysis
Frequency domain analysis
Environmental impact

Post-routing layer assignment for double patterning with timing critical paths consideration

Sun, J., Lu, Y., Zhou, H., Yan, C. & Zeng, X., Mar 1 2013, In : Integration, the VLSI Journal. 46, 2, p. 153-164 12 p.

Research output: Contribution to journalArticle

Wire
Benchmarking
Lithography
Masks
Capacitance

SmipRef: An efficient method for multi-domain clock skew scheduling

Zhi, Y., Luk, W. S., Zhou, H. & Zeng, X., Sep 1 2013, In : Integration, the VLSI Journal. 46, 4, p. 392-403 12 p.

Research output: Contribution to journalArticle

Clocks
Scheduling
Sequential circuits
Flip flop circuits
Linear programming
2011
5 Citations (Scopus)

Binning optimization for transparently-latched circuits

Gong, M., Zhou, H., Li, L., Tao, J. & Zeng, X., Feb 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 2, p. 270-283 14 p., 5689369.

Research output: Contribution to journalArticle

Profitability
Networks (circuits)
Bins
Clocks
Costs
8 Citations (Scopus)

Efficient approximation algorithms for chemical mechanical polishing dummy fill

Feng, C., Zhou, H., Yan, C., Tao, J. & Zeng, X., Mar 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 3, p. 402-415 14 p., 5715601.

Research output: Contribution to journalArticle

Chemical mechanical polishing
Approximation algorithms
Capacitance
Delay circuits
Heuristic methods

FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis

Das, D., Shebaita, A., Zhou, H., Ismail, Y. & Killpack, K., Mar 1 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 3, p. 443-456 14 p., 5352252.

Research output: Contribution to journalArticle

SPICE
17 Citations (Scopus)

MSV-driven floorplanning

Ma, Q., Qian, Z., Young, E. F. Y. & Zhou, H., Aug 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 8, p. 1152-1162 11 p., 5956869.

Research output: Contribution to journalArticle

Electric potential
Costs
Networks (circuits)
Electric power utilization
Subroutines
2010
4 Citations (Scopus)

Multicore parallelization of min-cost flow for CAD applications

Lu, Y., Zhou, H., Shang, L. & Zeng, X., Oct 1 2010, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 10, p. 1546-1557 12 p., 5580222.

Research output: Contribution to journalArticle

Computer aided design
Costs
VLSI circuits
Electric potential
Microprocessor chips

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

Das, D., Killpack, K., Kashyap, C., Jas, A. & Zhou, H., Mar 1 2010, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 3, p. 466-478 13 p., 5419240.

Research output: Contribution to journalArticle

Microprocessor chips
2009
6 Citations (Scopus)

A timing-dependent power estimation framework considering coupling

Khalil, D. E., Sinha, D., Zhou, H. & Ismail, Y., Jun 1 2009, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17, 6, p. 843-847 5 p., 4926126.

Research output: Contribution to journalArticle

Electric power utilization
Capacitance
Combinatorial circuits
Energy dissipation
Networks (circuits)
20 Citations (Scopus)

Gate sizing by Lagrangian relaxation revisited

Wang, J., Das, D. & Zhou, H., Jul 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 7, p. 1071-1084 14 p., 5075815.

Research output: Contribution to journalArticle

Clocks
Sequential circuits
Costs
2008
5 Citations (Scopus)
Heuristic algorithms
29 Citations (Scopus)
6 Citations (Scopus)

Fast estimation of timing yield bounds for process variations

Chen, R. & Zhou, H., Mar 1 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 3, p. 241-248 8 p., 4453949.

Research output: Contribution to journalArticle

Fabrication

Optimizing wirelength and routability by searching alternative packings in floorplanning

Sham, C. W., Young, E. F. Y. & Zhou, H., Jan 1 2008, In : ACM Transactions on Design Automation of Electronic Systems. 13, 1, 21.

Research output: Contribution to journalArticle

Costs
Planning
Networks (circuits)
2007
31 Citations (Scopus)

Advances in computation of the maximum of a set of Gaussian random variables

Sinha, D., Zhou, H. & Shenoy, N. V., Aug 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 8, p. 1522-1533 12 p.

Research output: Contribution to journalArticle

Random variables
Table lookup
Taylor series
1 Citation (Scopus)

An Effective algorithm for buffer insertion in general circuits based on network flow

Chen, R. & Zhou, H., Nov 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 11, p. 2069-2073 5 p., 4351998.

Research output: Contribution to journalArticle

Combinatorial circuits
Networks (circuits)
Costs
24 Citations (Scopus)

Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

Mallik, A., Sinha, D., Banerjee, P. & Zhou, H., Mar 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 3, p. 447-454 8 p.

Research output: Contribution to journalArticle

Integrated circuits
Electric power utilization
Application programs
Embedded systems
Automation
6 Citations (Scopus)
Antennas
Oxides
Dynamic programming
Wire
Plasmas
1 Citation (Scopus)

Tradeoff between latch and flop for min-period sequential circuit designs with crosstalk

Lin, C. & Zhou, H., Jul 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 7, p. 1222-1232 11 p., 4237236.

Research output: Contribution to journalArticle

Sequential circuits
Flip flop circuits
Crosstalk
Heuristic algorithms
Clocks
20 Citations (Scopus)

Unified incremental physical-level and high-level synthesis

Gu, Z., Wang, J., Dick, R. P. & Zhou, H., Sep 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 9, p. 1576-1588 13 p.

Research output: Contribution to journalArticle

Electric power utilization
VLSI circuits
Program processors
Integrated circuits
Systems analysis
2006
2 Citations (Scopus)

An efficient data structure for maxplus merge in dynamic programming

Ruiming, C. & Zhou, H., Dec 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 12, p. 3004-3009 6 p.

Research output: Contribution to journalArticle

Dynamic programming
Data structures
Merging
2 Citations (Scopus)

Clustering for processing rate optimization

Lin, C., Wang, J. & Zhou, H., Nov 1 2006, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14, 11, p. 1264-1275 12 p.

Research output: Contribution to journalArticle

Processing
Clocks
Throughput
Logic Synthesis
1 Citation (Scopus)

Gate-size optimization under timing constraints for coupling-noise reduction

Sinha, D. & Zhou, H., Jun 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 6, p. 1064-1074 11 p.

Research output: Contribution to journalArticle

Noise abatement
Networks (circuits)
Electric power utilization
4 Citations (Scopus)

Optimal wire retiming without binary search

Lin, C. & Zhou, H., Sep 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 9, p. 1577-1588 12 p., 1673735.

Research output: Contribution to journalArticle

Wire
Flip flop circuits
Clocks
Polynomials
10 Citations (Scopus)

Statistical timing analysis with coupling

Sinha, D. & Zhou, H., Dec 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 12, p. 2965-2974 10 p.

Research output: Contribution to journalArticle

Gaussian distribution
Networks (circuits)
Monte Carlo simulation
11 Citations (Scopus)

Statistical timing verification for transparently latched circuits

Chen, R. & Zhou, H., Sep 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 9, p. 1847-1855 9 p., 1673755.

Research output: Contribution to journalArticle

Networks (circuits)
Heuristic algorithms
Clocks
Monte Carlo simulation
Integrated circuit design
18 Citations (Scopus)

Statistical timing yield optimization by gate sizing

Sinha, D., Shenoy, N. V. & Zhou, H., Oct 1 2006, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14, 10, p. 1140-1146 7 p., 1715350.

Research output: Contribution to journalArticle

Networks (circuits)
Microelectronics
Experiments
2005
21 Citations (Scopus)

Spanning graph-based nonrectilinear steiner tree algorithms

Zhu, Q., Zhou, H., Jing, T., Hong, X. L. & Yang, Y., Jul 1 2005, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24, 7, p. 1066-1075 10 p.

Research output: Contribution to journalArticle

Wire
VLSI circuits
Crosstalk
Substitution reactions
Capacitance
4 Citations (Scopus)

Wire retiming as fixpoint computation

Lin, C. & Zhou, H., Dec 1 2005, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13, 12, p. 1340-1348 9 p.

Research output: Contribution to journalArticle

Wire
Flip flop circuits
Macros
Pipelines
Networks (circuits)
2004
27 Citations (Scopus)
Heuristic algorithms
Computer aided design
16 Citations (Scopus)

Retiming for wire pipelining in system-on-chip

Zhou, H. & Lin, C., Sep 1 2004, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23, 9, p. 1338-1345 8 p.

Research output: Contribution to journalArticle

Wire
Communication
Flip flop circuits
Clocks
Pipelines
2003
7 Citations (Scopus)

BDD based procedures for a theory of equality with uninterpreted functions

Goel, A., Sajid, K., Zhou, H., Aziz, A. & Singhal, V., May 1 2003, In : Formal Methods in System Design. 22, 3, p. 205-224 20 p.

Research output: Contribution to journalArticle

Equality
Logic
Hardware
Symbolic Methods
Hardware Design
20 Citations (Scopus)
Crosstalk
Coupled circuits
Networks (circuits)
2002
32 Citations (Scopus)

Efficient minimum spanning tree construction without Delaunay triangulation

Zhou, H., Shenoy, N. & Nicholls, W., Mar 16 2002, In : Information Processing Letters. 81, 5, p. 271-276 6 p.

Research output: Contribution to journalArticle

Delaunay triangulation
Minimum Spanning Tree
Triangulation
Graph in graph theory
Sweep
5 Citations (Scopus)

Track assignment: A desirable intermediate step between global routing and detailed routing

Batterywala, S., Shenoy, N., Nicholls, W. & Zhou, H., Jan 1 2002, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 59-66 8 p.

Research output: Contribution to journalArticle

Electric wiring
Routing algorithms
Routers
Costs
2001
5 Citations (Scopus)

Buffer minimization in pass transistor logic

Zhou, H. & Aziz, A., May 1 2001, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20, 5, p. 693-697 5 p.

Research output: Contribution to journalArticle

Transistors
Logic circuits
Networks (circuits)
Metals
2000
17 Citations (Scopus)

Optimal low power XOR gate decomposition

Zhou, H. & Wong, D. F., Jan 1 2000, In : Proceedings - Design Automation Conference. p. 104-107 4 p.

Research output: Contribution to journalArticle

Decomposition
Optimal design
Integrated circuit design
41 Citations (Scopus)

Simultaneous routing and buffer insertion with restrictions on buffer locations

Zhou, H., Wong, D. R., Liu, I. M. & Aziz, A., Jul 1 2000, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19, 7, p. 819-824 6 p.

Research output: Contribution to journalArticle

Macros
Polynomials
Wire
1999
7 Citations (Scopus)
Topology
Costs