If you made any changes in Pure these will be visible here soon.

Personal profile

Research Interests

Ultra-low power/voltage design for VLSI and mixed-signal ICs; Efficient power, clock management with hardware and software collaboration; Emerging device modeling, design and integration

Education/Academic qualification

Electrical and Computer Engineering, PhD, University of Minnesota

20032008

MS, Texas A&M University

20012003

BS, Tsinghua University

Fingerprint Dive into the research topics where Jie Gu is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 4 Similar Profiles

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Grants

  • Research Output

    • 578 Citations
    • 39 Conference contribution
    • 18 Article
    • 1 Conference article

    A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators

    Jia, T., Ju, Y. & Gu, J., Feb 2020, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc., p. 482-484 3 p. 9063062. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2020-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training

    Wei, Y., Cao, Q., Gu, J., Otseidu, K. & Hargrove, L., Mar 2020, 2020 IEEE Custom Integrated Circuits Conference, CICC 2020. Institute of Electrical and Electronics Engineers Inc., 9075910. (Proceedings of the Custom Integrated Circuits Conference; vol. 2020-March).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

    Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations

    19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

    Chen, Z. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 324-326 3 p. 8662340. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations