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Personal profile

Research Interests

Ultra-low power/voltage design for VLSI and mixed-signal ICs; Efficient power, clock management with hardware and software collaboration; Emerging device modeling, design and integration

Education/Academic qualification

Electrical and Computer Engineering, PhD, University of Minnesota

20032008

MS, Texas A&M University

20012003

BS, Tsinghua University

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  • 2 Similar Profiles
Clocks Engineering & Materials Science
Networks (circuits) Engineering & Materials Science
Electric potential Engineering & Materials Science
Memristors Engineering & Materials Science
Transistors Engineering & Materials Science
Microprocessor chips Engineering & Materials Science
Capacitors Engineering & Materials Science
Damping Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Grants 2015 2024

Research Output 2002 2019

  • 548 Citations
  • 37 Conference contribution
  • 17 Article
  • 1 Conference article

19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Pipelines
Error detection
Program processors
Networks (circuits)

19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

Chen, Z. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 324-326 3 p. 8662340. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Time series
Throughput
Engines
DNA
Microprocessor chips
Clocks
Phase locked loops
Energy conservation
Pipelines

A RRAM-based coarse grain reconfigurable array for neural network accelerators

Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
accelerators
Neural networks
logic
space storage

Digital compatible synthesis, placement and implementation of mixed-signal time-domain computing

Chen, Z., Zhou, H. & Gu, J., Jun 2 2019, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a67. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Placement
Time Domain
Synthesis
Computing
Analogue