If you made any changes in Pure, your changes will be visible here soon.

Personal profile

Research Interests

Ultra-low power/voltage design for VLSI and mixed-signal ICs; Efficient power, clock management with hardware and software collaboration; Emerging device modeling, design and integration

Education/Academic qualification

Electrical and Computer Engineering, PhD, University of Minnesota

20032008

MS, Texas A&M University

20012003

BS, Tsinghua University

Fingerprint Dive into the research topics where Jie Gu is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 13 Similar Profiles
Clocks Engineering & Materials Science
Networks (circuits) Engineering & Materials Science
Electric potential Engineering & Materials Science
Memristors Engineering & Materials Science
Transistors Engineering & Materials Science
Capacitors Engineering & Materials Science
Damping Engineering & Materials Science
Microprocessor chips Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Grants 2015 2024

Processing
Sensor nodes
Learning systems
Automation
Sensors
Distributed computer systems
Signal processing
Electronic equipment
Fusion reactions
Sensors
Clocks
Hardware
Calibration
Microprocessor chips
Energy conservation
Electronic equipment
X ray photoelectron spectroscopy
Semiconductor materials
Computer systems
Costs

Research Output 2002 2019

  • 524 Citations
  • 35 Conference contribution
  • 16 Article
  • 1 Conference article

19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

Jia, T., Joseph, R. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Pipelines
Error detection
Program processors
Networks (circuits)

19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

Chen, Z. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 324-326 3 p. 8662340. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Time series
Throughput
Engines
DNA

A RRAM-based coarse grain reconfigurable array for neural network accelerators

Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
accelerators
Neural networks
logic
space storage

Holistic Energy Management with μprocessor Co-Optimization in Fully Integrated Battery-Less IoTs

Hester, J. D., Jia, T. & Gu, J., Jan 17 2019, Proceedings - 31st IEEE International System on Chip Conference, SOCC 2018. Stan, M., Li, H., Bhatia, K., Sridhar, R. & Alioto, M. (eds.). IEEE Computer Society, p. 61-66 6 p. 8618523. (International System on Chip Conference; vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy harvesting
Energy management
Microprocessor chips
Voltage regulators
Harvesters

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Chen, Z., Zhou, H. & Gu, J., Jan 16 2019, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., p. 163-170 8 p. 8615684. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Logic circuits
Resource allocation
RRAM