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Personal profile

Research Interests

Ultra-low power/voltage design for VLSI and mixed-signal ICs; Efficient power, clock management with hardware and software collaboration; Emerging device modeling, design and integration

Education/Academic qualification

Electrical and Computer Engineering, PhD, University of Minnesota

20032008

MS, Texas A and M University

20012003

BS, Tsinghua University

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Grants

  • Research Output

    • 569 Citations
    • 37 Conference contribution
    • 18 Article
    • 1 Conference article

    19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

    Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

    Chen, Z. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 324-326 3 p. 8662340. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations
  • A RRAM-based coarse grain reconfigurable array for neural network accelerators

    Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Time-Domain Computing Accelerated Image Recognition Processor with Efficient Time Encoding and Non-Linear Logic Operation

    Chen, Z. & Gu, J., Nov 2019, In : IEEE Journal of Solid-State Circuits. 54, 11, p. 3226-3237 12 p., 8581434.

    Research output: Contribution to journalArticle