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Research Output 2002 2019

  • 542 Citations
  • 37 Conference contribution
  • 17 Article
  • 1 Conference article
2019

19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Pipelines
Error detection
Program processors
Networks (circuits)

19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

Chen, Z. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 324-326 3 p. 8662340. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Time series
Throughput
Engines
DNA
Microprocessor chips
Clocks
Phase locked loops
Energy conservation
Pipelines

A RRAM-based coarse grain reconfigurable array for neural network accelerators

Chen, Z., Zhou, H. & Gu, J., Feb 11 2019, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640182. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
accelerators
Neural networks
logic
space storage

Digital compatible synthesis, placement and implementation of mixed-signal time-domain computing

Chen, Z., Zhou, H. & Gu, J., Jun 2 2019, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a67. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Placement
Time Domain
Synthesis
Computing
Analogue

Holistic Energy Management with μprocessor Co-Optimization in Fully Integrated Battery-Less IoTs

Hester, J. D., Jia, T. & Gu, J., Jan 17 2019, Proceedings - 31st IEEE International System on Chip Conference, SOCC 2018. Stan, M., Li, H., Bhatia, K., Sridhar, R. & Alioto, M. (eds.). IEEE Computer Society, p. 61-66 6 p. 8618523. (International System on Chip Conference; vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy harvesting
Energy management
Microprocessor chips
Voltage regulators
Harvesters

Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries

Rezaei, A., Gu, J. & Zhou, H., Jul 1 2019, Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, p. 535-540 6 p. 8839487. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Foundries
Networks (circuits)
Semiconductor materials
Hardware

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Chen, Z., Zhou, H. & Gu, J., Jan 16 2019, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., p. 163-170 8 p. 8615684. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Logic circuits
Resource allocation
RRAM
2018

A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design

Chen, Z., Wang, H., Xie, G. & Gu, J., Oct 1 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 10, p. 2118-2131 14 p., 8401340.

Research output: Contribution to journalArticle

Electric potential
Flip flop circuits
Digital signal processors
Integrated circuits
Energy utilization
1 Citation (Scopus)

A Fully Integrated Buck Regulator with 2-GHz Resonant Switching for Low-Power Applications

Jia, T. & Gu, J., Sep 1 2018, In : IEEE Journal of Solid-State Circuits. 53, 9, p. 2663-2674 12 p., 8386797.

Research output: Contribution to journalArticle

Switching frequency
Clocks
Switches
Recovery
Networks (circuits)

A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications

Jia, T. & Gu, J., Dec 14 2018, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 179-182 4 p. 8579285. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Switching frequency
Energy efficiency
Resonators
Tuning
1 Citation (Scopus)

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation

Chen, Z. & Gu, J., Dec 14 2018, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 257-260 4 p. 8579259. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image recognition
Particle accelerators
Signal processing
Vector quantization
Feature extraction
2 Citations (Scopus)

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Jia, T., Joseph, R. E. & Gu, J., Oct 16 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 158-161 4 p. 8494244. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

microprocessors
clocks
Microprocessor chips
Clocks
coding
Image recognition
Vector quantization
Feature extraction
Image processing
Neural networks
2 Citations (Scopus)

Compiler-guided instruction-level clock scheduling for timing speculative processors

Fan, Y., Jia, T., Gu, J., Campanoni, S. & Joseph, R. E., Jun 24 2018, Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., a40. (Proceedings - Design Automation Conference; vol. Part F137710).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compiler
Clocks
Timing
Speculation
Scheduling
5 Citations (Scopus)

Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks

Rezaei, A., Shen, Y., Kong, S., Gu, J. & Zhou, H., Apr 19 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., p. 85-90 6 p. (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Foundries
Networks (circuits)
Combinatorial circuits
Semiconductor materials

Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion

Otseidu, K., Jia, T., Bryne, J., Hargrove, L. J. & Gu, J., Nov 5 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a120. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Distributed computer systems
Patient rehabilitation
Fusion reactions
Sensors
Electric wiring
1 Citation (Scopus)

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design

Kong, S., Zhou, H. & Gu, J., Dec 1 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 12, p. 2648-2660 13 p., 8368092.

Research output: Contribution to journalArticle

Networks (circuits)
Tuning
Memristors
Flip flop circuits
VLSI circuits
2017

(Invited) Software-guided greybox design methodology with integrated power and clock management

Jia, T., Fan, Y., Joseph, R. E. & Gu, J., Sep 27 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., p. 894-897 4 p. 8053068. (Midwest Symposium on Circuits and Systems; vol. 2017-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Software design
Microprocessor chips
Hardware
3 Citations (Scopus)

A 0.3-0.86V fully integrated buck regulator with 2GHz resonant switching for ultra-low power applications

Jia, T. & Gu, J., Aug 10 2017, 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., p. C208-C209 8008485

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric potential
Switching frequency
Tuning

Cell-to-array thermal-aware analysis of stacked RRAM

Luo, Y., Ogrenci-Memik, S. & Gu, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050966

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Temperature control
Hot Temperature
Temperature
Thin films
1 Citation (Scopus)

Exploiting accelerated aging effect for on-line configurability and hardware tracking

You, Y. & Gu, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 348-353 6 p. 7858347. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Aging of materials
Hardware
Transistors
Networks (circuits)
Processing
5 Citations (Scopus)

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management

Jia, T., Joseph, R. E. & Gu, J., Jun 18 2017, Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 48. (Proceedings - Design Automation Conference; vol. Part 128280).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design Methodology
Clocks
Hardware
Speedup
Hardware Design
1 Citation (Scopus)

Memristor-Based Clock Design and Optimization with In-Situ Tunability

Kong, S., Gu, J. & Zhou, H., Jul 20 2017, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Reis, R., Stan, M., Huebner, M. & Voros, N. (eds.). IEEE Computer Society, p. 427-432 6 p. 7987557. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Clocks
Tuning
Scheduling
Detectors
2016
5 Citations (Scopus)

Analysis and Design of Energy Efficient Time Domain Signal Processing

Chen, Z. & Gu, J., 2016, ISLPED '16 Proceedings of the 2016 International Symposium on Low Power Electronics and Design. ACM, p. 100-105 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Signal processing
Energy efficiency
Networks (circuits)
Electric potential
1 Citation (Scopus)

Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design

Wang, H., Xie, G. & Gu, J., 2016, ISLPED '16 Proceedings of the 2016 International Symposium on Low Power Electronics and Design. ACM, p. 22-27 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric potential
Low power electronics
Degradation
Statistical methods
Networks (circuits)
5 Citations (Scopus)

Exploration of associative power management with instruction governed operation for ultra-low power design

Jia, T., Fan, Y., Joseph, R. E. & Gu, J., Jun 5 2016, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 05-09-June-2016. a152

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-power Design
Power Management
Energy efficiency
Energy Efficiency
Regulator
2015
3 Citations (Scopus)

Exploration of self-healing circuits for timing resilient design using emerging memristor devices

Gu, J. & Li, J., Jan 1 2015, 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 1458-1461 4 p. 7168919

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memristors
Networks (circuits)
Tuning
Sequential circuits
Threshold voltage
2012
25 Citations (Scopus)

A 28 nm 0.6 v low power DSP for mobile applications

Ickes, N., Gammie, G., Sinangil, M. E., Rithe, R., Gu, J., Wang, A., Mair, H., Datla, S., Rong, B., Honnavara-Prasad, S., Ho, L., Baldwin, G., Buss, D., Chandrakasan, A. P. & Ko, U., Jan 1 2012, In : IEEE Journal of Solid-State Circuits. 47, 1, p. 35-46 12 p., 6081953.

Research output: Contribution to journalArticle

Electric potential
Static random access storage
Mobile devices
Transistors
System-on-chip
21 Citations (Scopus)

The effect of random dopant fluctuations on logic timing at low voltage

Rithe, R., Chou, S., Gu, J., Wang, A., Datla, S., Gammie, G., Buss, D. & Chandrakasan, A., May 1 2012, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 5, p. 911-924 14 p., 5740397.

Research output: Contribution to journalArticle

Probability density function
Doping (additives)
Electric potential
Random variables
Computer aided design
2011
30 Citations (Scopus)

A 28nm 0.6V low-power DSP for mobile applications

Gammie, G., Ickes, N., Sinangil, M. E., Rithe, R., Gu, J., Wang, A., Mair, H., Datla, S., Rong, B., Honnavara-Prasad, S., Ho, L., Baldwin, G., Buss, D., Chandrakasan, A. P. & Ko, U., May 12 2011, 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. p. 132-133 2 p. 5746251. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Electric potential
Interfaces (computer)
Macros
Data storage equipment
2 Citations (Scopus)

Cell library characterization at low voltage using non-linear operating point analysis of local variations

Rithe, R., Chou, S., Gu, J., Wang, A., Datla, S., Gammie, G., Buss, D. & Chandrakasan, A., Mar 25 2011, Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. p. 112-117 6 p. 5718787. (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Probability density function
Electric potential
SPICE
Doping (additives)
2010
16 Citations (Scopus)

Circuit design and modeling techniques for enhancing the clock-data compensation effect under resonant supply noise

Jiao, D., Gu, J. & Kim, C. H., Oct 1 2010, In : IEEE Journal of Solid-State Circuits. 45, 10, p. 2130-2141 12 p., 5584967.

Research output: Contribution to journalArticle

Clocks
Networks (circuits)
Jitter
Compensation and Redress
12 Citations (Scopus)

Non-linear operating point statistical analysis for local variations in logic timing at low voltage

Rithe, R., Gu, J., Wang, A., Datla, S., Gammie, G., Buss, D. & Chandrakasan, A., Jun 9 2010, DATE 10 - Design, Automation and Test in Europe. p. 965-968 4 p. 5456911. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Probability density function
Statistical methods
Electric potential
SPICE
Computer aided design
2009
4 Citations (Scopus)

Circuit techniques for enhancing the clock data compensation effect under resonant supply noise

Jiao, D., Gu, J. & Kim, C. H., Dec 1 2009, 2009 IEEE Custom Integrated Circuits Conference, CICC '09. p. 29-32 4 p. 5280918. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Jitter
Pipelines
Compensation and Redress
31 Citations (Scopus)

Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ICs

Gu, J., Harjani, R. & Kim, C. H., Feb 1 2009, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17, 2, p. 292-301 10 p.

Research output: Contribution to journalArticle

Digital integrated circuits
Capacitors
Networks (circuits)
Noise generators
Operational amplifiers
1 Citation (Scopus)

Modeling, analysis, and application of leakage induced damping effect for power supply integrity

Gu, J., Keane, J. & Kim, C. H., Jan 1 2009, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17, 1, p. 128-136 9 p., 4703195.

Research output: Contribution to journalArticle

Damping
Leakage currents
Static random access storage
Resistors
Transistors
28 Citations (Scopus)

On-chip supply noise regulation using a low-power digital switched decoupling capacitor circuit

Gu, J., Eom, H. & Kim, C. H., Jun 1 2009, In : IEEE Journal of Solid-State Circuits. 44, 6, p. 1765-1775 11 p., 4982870.

Research output: Contribution to journalArticle

Capacitors
Networks (circuits)
Microprocessor chips
Charge transfer
Electric power utilization
6 Citations (Scopus)

Sleep transistor sizing and adaptive control for supply noise minimization considering resonance

Gu, J., Eom, H., Keane, J. & Kim, C. H., Sep 1 2009, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17, 9, p. 1203-1211 9 p., 4801591.

Research output: Contribution to journalArticle

Transistors
Networks (circuits)
Sleep
2008
31 Citations (Scopus)

A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Kil, J., Gu, J. & Kim, C. H., Apr 1 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 4, p. 456-465 10 p., 4459695.

Research output: Contribution to journalArticle

Networks (circuits)
Clocks
Electric potential
Clock distribution networks
Temperature
5 Citations (Scopus)

Enhancing beneficial jitter using phase-shifted clock distribution

Jiao, D., Gu, J., Jain, P. & Kim, C. H., Dec 17 2008, ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. p. 21-26 6 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jitter
Clocks
Phase shift
Analytical models
Capacitors
14 Citations (Scopus)

Statistical leakage estimation of double gate FinFET devices considering the width quantization property

Gu, J., Keane, J., Sapatnekar, S. & Kim, C. H., Feb 1 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 2, p. 206-209 4 p.

Research output: Contribution to journalArticle

Leakage currents
Networks (circuits)
FinFET
Monte Carlo simulation
2007
22 Citations (Scopus)

A switched decoupling capacitor circuit for on-chip supply resonance damping

Gu, J., Eom, H. & Kim, C. H., Dec 1 2007, 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 126-127 2 p. 4342684. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Capacitors
Damping
Networks (circuits)
Tuning
2 Citations (Scopus)

Sleep transistor sizing and control for resonant supply noise damping

Gu, J., Eom, H. & Kim, C. H., Dec 17 2007, ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. p. 80-85 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors
Damping
Sleep
12 Citations (Scopus)

Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift

Gu, J., Sapatnekar, S. S. & Kim, C., Aug 2 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. p. 87-92 6 p. 4261149

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Threshold voltage
Doping (additives)
Static random access storage
Error analysis
Networks (circuits)
2006
8 Citations (Scopus)

A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Kil, J., Gu, J. & Kim, C. H., Dec 1 2006, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. Vol. 2006. p. 67-72 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clock distribution networks
Clocks
Transistors
Wire
Networks (circuits)
20 Citations (Scopus)

Distributed active decoupling capacitors for on-chip supply noise cancellation in digital VLSI circuits

Gu, J., Harjani, R. & Kim, C., Dec 1 2006, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 216-217 2 p. 1705387. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI circuits
Digital circuits
Capacitors
Noise generators
Networks (circuits)
2 Citations (Scopus)

Modeling and analysis of leakage induced damping effect in low voltage LSIs

Jie, G., Keane, J. & Kim, C., Dec 1 2006, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. Vol. 2006. p. 382-387 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Damping
Electric potential
Leakage currents
Transistors
Physics
24 Citations (Scopus)

Width quantization aware FinFET circuit design

Gu, J., Keane, J., Sapatnekar, S. & Kim, C., Dec 1 2006, Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006. p. 337-340 4 p. 4114973. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Logic circuits
Leakage currents
FinFET
Monte Carlo simulation
2005
55 Citations (Scopus)

Charging process and Coulomb-force-directed printing of nanoparticles with sub-100-nm lateral resolution

Barry, C. R., Gu, J. & Jacobs, H. O., Oct 1 2005, In : Nano letters. 5, 10, p. 2078-2084 7 p.

Research output: Contribution to journalArticle

printing
charging
Printing
Nanoparticles
nanoparticles