• 998 Citations
20012022

Research output per year

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Personal profile

Research Interests

Computer architecture, microprocessor design for reliability and variability tolerance, power-aware computing.

Education/Academic qualification

Electrical and Computer Engineering, BS, Carnegie Mellon University

Electrical Engineering, MA, Princeton University

Electrical Engineering, PhD, Princeton University

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Grants

Research Output

  • 998 Citations
  • 25 Conference contribution
  • 8 Article
  • 2 Conference article

19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations
  • Time squeezing for tiny devices

    Fan, Y., Campanoni, S. & Joseph, R. E., Jun 22 2019, ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., p. 657-670 14 p. (Proceedings - International Symposium on Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations

    An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

    Jia, T., Joseph, R. E. & Gu, J., Oct 16 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 158-161 4 p. 8494244. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2 Scopus citations

    Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches

    Yan, C. & Joseph, R. E., Oct 1 2018, MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Scopus citations