Grants per year
Personal profile
Research Interests
Computer architecture, microprocessor design for reliability and variability tolerance, power-aware computing.
Education/Academic qualification
Electrical and Computer Engineering, BS, Carnegie Mellon University
Electrical Engineering, MA, Princeton University
Electrical Engineering, PhD, Princeton University
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Dive into the research topics where Russell E Joseph is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Grants
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SHF: Small: The Compiler-Architecture Solution to the Data Dependent, Circuit-Level Critical-Paths Variations
10/1/19 → 9/30/22
Project: Research project
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SHF: Small: Greybox Computing: An Associative Computing Methodology with Instruction Directed Power and Clock Management
7/1/16 → 6/30/21
Project: Research project
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REU Supplement for "SHF: Small: Integrating Compiler and Architecture Design to Boost Timing Speculation"
9/1/11 → 8/31/16
Project: Research project
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SHF: Small: Integrating Compiler and Architecture Design to Boost Timing Speculation
9/1/11 → 8/31/16
Project: Research project
Research Output
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An adaptive clock scheme exploiting instruction-based dynamic timing slack for a gpgpu architecture
Jia, T., Wei, Y., Joseph, R. & Gu, J., Aug 2020, In: IEEE Journal of Solid-State Circuits. 55, 8, p. 2259-2269 11 p., 9044316.Research output: Contribution to journal › Article › peer-review
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NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance
Jia, T., Ju, Y., Joseph, R. & Gu, J., Oct 2020, Proceedings - 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020. IEEE Computer Society, p. 1097-1109 13 p. 9251958. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; vol. 2020-October).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution
Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
3 Scopus citations -
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor
Jia, T., Joseph, R. E. & Gu, J., Aug 1 2019, In: IEEE Journal of Solid-State Circuits. 54, 8, p. 2327-2338 12 p., 8716516.Research output: Contribution to journal › Article › peer-review
3 Scopus citations -
Time squeezing for tiny devices
Fan, Y., Campanoni, S. & Joseph, R. E., Jun 22 2019, ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., p. 657-670 14 p. (Proceedings - International Symposium on Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
3 Scopus citations