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Research Output 2001 2019

  • 959 Citations
  • 25 Conference contribution
  • 8 Article
  • 2 Conference article
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Conference contribution
2019

19.4 An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

Jia, T., Joseph, R. E. & Gu, J., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 318-320 3 p. 8662389. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Pipelines
Error detection
Program processors
Networks (circuits)

Time squeezing for tiny devices

Fan, Y., Campanoni, S. & Joseph, R. E., Jun 22 2019, ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., p. 657-670 14 p. (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Embedded systems
Transparency
Energy conservation
Energy utilization
2018
2 Citations (Scopus)

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Jia, T., Joseph, R. E. & Gu, J., Oct 16 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 158-161 4 p. 8494244. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

microprocessors
clocks
Microprocessor chips
Clocks
coding

Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches

Yan, C. & Joseph, R. E., Oct 1 2018, MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cocoa
Error correction
Electric potential
Static random access storage
Dynamic random access storage
2 Citations (Scopus)

Compiler-guided instruction-level clock scheduling for timing speculative processors

Fan, Y., Jia, T., Gu, J., Campanoni, S. & Joseph, R. E., Jun 24 2018, Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., a40. (Proceedings - Design Automation Conference; vol. Part F137710).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compiler
Clocks
Timing
Speculation
Scheduling
2017

(Invited) Software-guided greybox design methodology with integrated power and clock management

Jia, T., Fan, Y., Joseph, R. E. & Gu, J., Sep 27 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., p. 894-897 4 p. 8053068. (Midwest Symposium on Circuits and Systems; vol. 2017-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Software design
Microprocessor chips
Hardware
5 Citations (Scopus)

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management

Jia, T., Joseph, R. E. & Gu, J., Jun 18 2017, Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 48. (Proceedings - Design Automation Conference; vol. Part 128280).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design Methodology
Clocks
Hardware
Speedup
Hardware Design
2016
2 Citations (Scopus)

Enabling deep voltage scaling in delay sensitive L1 caches

Yan, C. & Joseph, R. E., Sep 29 2016, Proceedings - 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2016. Institute of Electrical and Electronics Engineers Inc., p. 192-202 11 p. 7579741. (Proceedings - 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Electric potential
Electric power utilization
Voltage scaling
5 Citations (Scopus)

Exploration of associative power management with instruction governed operation for ultra-low power design

Jia, T., Fan, Y., Joseph, R. E. & Gu, J., Jun 5 2016, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 05-09-June-2016. a152

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-power Design
Power Management
Energy efficiency
Energy Efficiency
Regulator
2015
1 Citation (Scopus)

Embedded system and application aware design of deregulated energy delivery systems

He, X., Dick, R. P. & Joseph, R. E., Nov 10 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015. Institute of Electrical and Electronics Engineers Inc., p. 1-10 10 p. 7324537. (2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Electric potential
Deregulation
Printed circuit boards
Voltage control
2012

Spatially-and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging

He, X., Dick, R. P. & Joseph, R. E., Nov 19 2012, CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK. p. 235-244 10 p. (CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scavenging
Sensor networks
Wireless sensor networks
Network protocols
Toxic materials
2011
2 Citations (Scopus)

Efficient parameter variation sampling for architecture simulations

Lu, F., Joseph, R. E., Trajcevski, G. & Liu, S., May 31 2011, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. p. 1578-1583 6 p. 5763250. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sampling
Multiresolution analysis
Computer architecture
Networks (circuits)
Computational complexity
20 Citations (Scopus)

Exploring circuit timing-aware language and compilation

Hoang, G., Findler, R. & Joseph, R. E., Mar 31 2011, ASPLOS XVI - 16th International Conference on Architectural Support for Programming Languages and Operating Systems. p. 345-355 11 p. (International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Timing circuits
Networks (circuits)
Innovation
Recovery
Costs
31 Citations (Scopus)

Identifying and predicting timing-critical instructions to boost timing speculation

Xin, J. & Joseph, R. E., Dec 1 2011, MICRO 44 - Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture. p. 128-139 12 p. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy efficiency
Tuning
Pipelines
Hardware
Recovery
2009
22 Citations (Scopus)

Process variation characterization of chip-level multiprocessors

Lide, Z., Bai, L. S., Dick, R. P., Li, S. & Joseph, R. E., Nov 10 2009, 2009 46th ACM/IEEE Design Automation Conference, DAC 2009. p. 694-697 4 p. 5227108

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Process Variation
Multiprocessor
Chip
Power Consumption
Task Assignment
2008
67 Citations (Scopus)

Multi-optimization power management for chip multiprocessors

Meng, K., Joseph, R. E., Dick, R. P. & Shang, L., Dec 1 2008, PACT'08: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. p. 177-186 10 p. (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chip multiprocessors
Power Management
Optimization
Power Saving
Trial and error
2007
13 Citations (Scopus)

Modeling and characterizing power variability in multicore architectures

Meng, K., Huebbers, F., Joseph, R. E. & Ismail, Y., Dec 17 2007, ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software. p. 146-157 12 p. 4211031. (ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SPICE
Statistical methods
Networks (circuits)
5 Citations (Scopus)

Power deregulation: Eliminating off-chip voltage regulation circuitry from embedded systems

Kim, S., Dick, R. P. & Joseph, R. E., Dec 1 2007, CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. p. 105-110 6 p. (CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deregulation
Embedded systems
Voltage control
Electrolytic capacitors
Voltage regulators
126 Citations (Scopus)

Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

Gupta, M. S., Oatley, J. L., Joseph, R. E., Wei, G. Y. & Brooks, D. M., Sep 4 2007, Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. p. 624-629 6 p. 4211868. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microprocessor chips
Energy dissipation
Electric potential
Power management
Voltage scaling
2006

Physical Resource Matching Under Power Asymmetry

Meng, K., Huebbers, F., Joseph, R. & Ismail, Y., 2006, Physical Resource Matching Under Power Asymmetry.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

51 Citations (Scopus)

Process variation aware cache leakage management

Meng, K. & Joseph, R. E., Dec 1 2006, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. Vol. 2006. p. 262-267 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leakage currents
Doping (additives)
Hardware
Fabrication
Oxides
2004
9 Citations (Scopus)

Spectral analysis for characterizing program power and performance

Joseph, R., Martonosi, M. & Hu, Z., Jun 14 2004, 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS. p. 151-160 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fourier analysis
Spectrum analysis
Voltage control
Temperature
Hot Temperature
2003
11 Citations (Scopus)

Considering the energy consumption of mobile storage alternatives

Zheng, F., Garg, N., Sobti, S., Zhang, C., Joseph, R. E., Krishnamurthy, A. & Wang, R. Y., Jan 1 2003, Proceedings of the 11th IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer Telecommunications Systems, MASCOTS 2003. IEEE Computer Society, p. 36-45 10 p. 1240640. (Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy Consumption
File System
Energy utilization
Alternatives
Two Dimensions
101 Citations (Scopus)

Control Techniques to Eliminate Voltage Emergencies in High Performance Processors

Joseph, R., Brooks, D. & Martonosi, M., 2003, Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. IEEE Computer Society Press

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2001
161 Citations (Scopus)

Run-time power estimation in high performance microprocessors

Joseph, R. & Martonosi, M., Jan 1 2001, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. p. 135-140 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Microprocessor chips
Computer architecture
Computer hardware
Electric power utilization