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Research Output 2000 2019

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Article
2019

A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in datapaths

Del Barrio, A. A., Hermida, R. & Memik, S. O., Feb 1 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 2, p. 742-755 14 p., 8451942.

Research output: Contribution to journalArticle

Adders
Energy utilization
High level synthesis
2018
6 Citations (Scopus)

Machine Learning-Based Temperature Prediction for Runtime Thermal Management Across System Components

Zhang, K., Guliani, A., Memik, S. O., Memik, G., Yoshii, K., Sankaran, R. & Beckman, P., Feb 1 2018, In : IEEE Transactions on Parallel and Distributed Systems. 29, 2, p. 405-419 15 p., 7995115.

Research output: Contribution to journalArticle

Temperature control
Learning systems
Temperature
Linear regression
Neural networks

Multi-Vdd design for content addressable memories (CAM): A power-delay optimization analysis

Joshi, S., Li, D., Memik, S. O., Deptuch, G., Hoff, J., Jindariani, S., Liu, T., Olsen, J. & Tran, N., Sep 1 2018, In : Journal of Low Power Electronics and Applications. 8, 3, 25.

Research output: Contribution to journalArticle

Associative storage
Electric power utilization
Foundries
Fabrication
Testing
2017
1 Citation (Scopus)

End-to-End Analysis of Integration for Thermocouple-Based Sensors into 3-D ICs

Li, D., Joshi, S., Kim, J. H. & Memik, S. O., Sep 1 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 9, p. 2498-2511 14 p., 7929379.

Research output: Contribution to journalArticle

Thermocouples
Integrated circuits
Sensors
Silicon
Hot Temperature
2016
5 Citations (Scopus)

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

Barrio, A. A. D., Hermida, R. & Memik, S. O., Nov 1 2016, In : IEEE Transactions on Computers. 65, 11, p. 3251-3264 14 p., 7406747.

Research output: Contribution to journalArticle

Multiplier
Partial
Adders
Percent
Encoder
2014
7 Citations (Scopus)

Improving circuit performance with multispeculative additive trees in high-level synthesis

Del Barrio, A. A., Hermida, R., Memik, S. O., Mendías, J. M. & Molina, M. C., Jan 1 2014, In : Microelectronics Journal. 45, 11, p. 1470-1479 10 p.

Research output: Contribution to journalArticle

Networks (circuits)
synthesis
predictions
Experiments
penalties
2013
2 Citations (Scopus)

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

Del Barrio, A. A., Memik, S. O., Molina, M. C., Mendías, J. M. & Hermida, R., Mar 1 2013, In : Integration, the VLSI Journal. 46, 2, p. 119-130 12 p.

Research output: Contribution to journalArticle

Networks (circuits)
High level synthesis
3 Citations (Scopus)

Exploring super-resolution implementations across multiple platforms

Leung, B. & Memik, S. O., Nov 4 2013, In : Eurasip Journal on Advances in Signal Processing. 2013, 1, 116.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Hardware
Bandwidth
Video streaming
MATLAB
4 Citations (Scopus)

Theory and analysis for optimization of on-chip thermoelectric cooling systems

Long, J., Li, D., Memik, S. O. & Ulgen, S., Sep 30 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 10, p. 1628-1632 5 p., 6601030.

Research output: Contribution to journalArticle

Cooling systems
Cooling
Linear algebra
Bias currents
Eigenvalues and eigenfunctions
2012
23 Citations (Scopus)

Multispeculative addition applied to datapath synthesis

Del Barrio, A. A., Hermida, R., Memik, S. O., Mendias, J. M. & Molina, M. C., Nov 26 2012, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 12, p. 1817-1830 14 p., 6349430.

Research output: Contribution to journalArticle

Adders
Digital circuits
Signal processing
Electric power utilization
2011
22 Citations (Scopus)

A distributed controller for managing speculative functional units in high level synthesis

Del Barrio, A. A., Memik, S. O., Molina, M. C., Mendias, J. M. & Hermida, R., Mar 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 3, p. 350-363 14 p., 5715599.

Research output: Contribution to journalArticle

Controllers
Scheduling
High level synthesis
14 Citations (Scopus)

Thermal sensing with lithographically patterned bimetallic thin-film thermocouples

Varrenti, A. R., Zhou, C., Klock, A. G., Chyung, S. H., Long, J., Memik, S. O. & Grayson, M., Jun 1 2011, In : IEEE Electron Device Letters. 32, 6, p. 818-820 3 p., 5763748.

Research output: Contribution to journalArticle

Thermocouples
Seebeck coefficient
Thin films
Temperature sensors
Thermal load
2010
13 Citations (Scopus)

A fast heuristic algorithm for multidomain clock skew scheduling

Ni, M. & Ogrenci Memik, S., Apr 1 2010, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 4, p. 630-637 8 p., 5153125.

Research output: Contribution to journalArticle

Heuristic algorithms
Clocks
Scheduling
Clock distribution networks
Networks (circuits)
2 Citations (Scopus)

An approach for adaptive DRAM temperature and power management

Liu, S., Zhang, Y., Ogrenci Memik, S. & Memik, G., Apr 1 2010, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 4, p. 684-688 5 p., 5075522.

Research output: Contribution to journalArticle

Dynamic random access storage
Electric power utilization
Temperature
Power management
Throughput
26 Citations (Scopus)

Placement and Floorplanning in Dynamically Reconfigurable FPGAs

Montone, A., Santambrogio, M. D., Sciuto, D., Ogrenci Memik, S. & Memik, S. O., Nov 2010, In : ACM Transactions on Reconfigurable Technology and Systems (TRETS). 4, p. 1-34

Research output: Contribution to journalArticle

8 Citations (Scopus)

SACTA: A self-adjusting clock tree architecture for adapting to thermal-induced delay variation

Long, J., Ku, J. C., Ogrenci Memik, S. & Ismail, Y., Sep 1 2010, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 9, p. 1323-1336 14 p., 5282522.

Research output: Contribution to journalArticle

Clocks
Temperature
Networks (circuits)
Timing circuits
Hot Temperature
2009

An ILP formulation for the Task Graph Scheduling Problem tailored to bi-dimensional Reconfigurable Architectures

Redaelli, F., Santambrogio, M., Ogrenci Memik, S. & Memik, S. O., 2009, In : International Journal on Reconfigurable Computing (IJRC). 2009, p. 1-12

Research output: Contribution to journalArticle

2008
1 Citation (Scopus)

A high-level clustering algorithm targeting dual Vdd FPGAs

Mukherjee, R., Liu, S., Memik, S. O. & Mondal, S., Sep 1 2008, In : ACM Transactions on Design Automation of Electronic Systems. 13, 4, 57.

Research output: Contribution to journalArticle

Clustering algorithms
Field programmable gate arrays (FPGA)
Electric potential
Electric power utilization
28 Citations (Scopus)
77 Citations (Scopus)

Optimizing thermal sensor allocation for microprocessors

Memik, S. O., Mukherjee, R., Ni, M. & Long, J., Mar 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 3, p. 516-527 12 p., 4454017.

Research output: Contribution to journalArticle

Microprocessor chips
Sensors
Hot Temperature
Thermal stress
Temperature control
2 Citations (Scopus)

Presynthesis area estimation of reconfigurable streaming accelerators

Memik, S. O., Bellas, N. & Mondal, S., Nov 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 11, p. 2027-2038 12 p., 4655563.

Research output: Contribution to journalArticle

Particle accelerators
Costs
Hardware
Experiments
58 Citations (Scopus)

Thermal monitoring mechanisms for chip multiprocessors

Long, J., Memik, S. O., Memik, G. & Mukherjee, R., Aug 1 2008, In : Transactions on Architecture and Code Optimization. 5, 2, 9.

Research output: Contribution to journalArticle

Monitoring
Sensors
Interpolation
Temperature control
Temperature
2006
19 Citations (Scopus)

An integrated approach to thermal management in high-level synthesis

Mukherjee, R. & Memik, S. O., Nov 1 2006, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14, 11, p. 1165-1173 9 p.

Research output: Contribution to journalArticle

Temperature control
Thermal effects
Temperature
Integrated circuits
Packaging
2005
13 Citations (Scopus)

A scheduling algorithm for optimization and early planning in high-level synthesis

Memik, S. O., Kastner, R., Bozorgzadeh, E. & Sarrafzadeh, M., Dec 1 2005, In : ACM Transactions on Design Automation of Electronic Systems. 10, 1, p. 33-57 25 p.

Research output: Contribution to journalArticle

Scheduling algorithms
Planning
Data flow graphs
Scheduling
Computational geometry

Early Quality Assessment for Low Power Behavioral Synthesis

Kursun, E., Mukherjee, R., Ogrenci Memik, S. & Memik, S. O., Dec 2005, In : Journal of Low Power Electronics (JOLPE). 1, p. 273-285

Research output: Contribution to journalArticle

3 Citations (Scopus)

On effective slack management in postscheduling phase

Srivastava, A., Memik, S. O., Choi, B. K. & Sarrafzadeh, M., Apr 1 2005, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24, 4, p. 645-652 8 p.

Research output: Contribution to journalArticle

Budget control
Clocks
Engines
Silicon
Experiments
2004
30 Citations (Scopus)

Routability-driven packing: Metrics and algorithms for cluster-based FPGAs

Bozorgzadeh, E., Memik, S. O., Yang, X. & Sarrafzadeh, M., Feb 1 2004, In : Journal of Circuits, Systems and Computers. 13, 1, p. 77-100 24 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Cost functions
Computer aided design
2002
22 Citations (Scopus)
Data flow graphs
Scheduling
Program processors
Experiments
145 Citations (Scopus)

Instruction generation for hybrid reconfigurable systems

Kastner, R., Kaplan, A., Ogrenci Memik, S. & Bozorgzadeh, E., Oct 1 2002, In : ACM Transactions on Design Automation of Electronic Systems. 7, 4, p. 605-627 23 p.

Research output: Contribution to journalArticle

Macros
Intellectual property core
2001
19 Citations (Scopus)

Fast Floorplanning for Effective Prediction and Construction

Ranjan, A., Bazargan, K., Ogrenci, S., Sarrafzadeh, M. & Memik, S. O., Apr 2001, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, p. 341-351

Research output: Contribution to journalArticle

17 Citations (Scopus)

Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Bazargan, K., Ogrenci, S. & Sarrafzadeh, M., Jan 1 2001, In : Proceedings - Design Automation Conference. p. 635-640 6 p.

Research output: Contribution to journalArticle

Scheduling
Data flow graphs
Computer hardware description languages
Field programmable gate arrays (FPGA)
Clocks
2000
1 Citation (Scopus)

Image analysis and partitioning for FPGA implementation of image restoration

Ogrenci, S., Bazargan, K. & Sarrafzadeh, M., Dec 1 2000, In : IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. p. 346-355 10 p.

Research output: Contribution to journalArticle

Image reconstruction
Image analysis
Field programmable gate arrays (FPGA)
Restoration
Statistical methods