The increasing complexity of deep neural networks (DNN) and their proliferating applications in embedded computing have pushed conventional computing architectures and technologies to their limits. As a result, there is an invigorated interest in exploring alternative technologies and computing architectures for DNN acceleration. In parallel, various new DNN layer styles, such as Hypernetworks and self-attention, are emerging to improve deep learning's computational efficiency. Therefore, a critical challenge for the next generation DNN accelerators is to exhibit high versatility in mapping these diverse set of traditional and emerging DNN layers efficiently into hardware circuits. A noticeable trend among emerging DNN layers is that, unlike classical DNN layers, multiple variables are simultaneously correlated. While the memristor is one of the most prevalent base devices for DNN acceleration, due to its two-electrode structure, it is only suited for classical DNN layers where two operands, namely weights and inputs, are processed at a time. Memristor grids thus cannot natively support emerging DNN layer operations where multiple operands, such as context, inputs, and weights, must be processed together. Addressing this unmet need, we propose Neuroplane - a novel DNN accelerator composed of a gate-tunable dual-gated memristive device, i.e., a dual-gated memtransistor. Dual-gated memtransistor crossbars in Neuroplane allow concurrent processing of multiple operands, thereby enabling high versatility in mapping traditional and emerging DNN layers. The gated crossbars can also be readily adapted to varying performance and energy constraints through on-demand tuning of resistance levels using gate voltages. Neuroplane also comprises microarchitecture-level novelties such as time-domain processing and crossbar-embedded data converters to mitigate traditional mixed-signal data converter overhead. A coherent collection of software and hardware-based correction techniques is proposed to minimize the impact of process variability. Different research initiatives are tied into two key deliverables: (1) We will develop fabrication processes for gate-tunable nanometer-scale dual-gated MoS2 crossbars in the first bottom-up research thrust; (2) We will create a novel simulation and mapping engine, NeuroplaneSIM, for automated DNN mapping and synthesis on dual-gated MoS2 crossbars in the second top-down research thrust. These complementary research thrusts will provide end-to-end interaction among fabrication processes, microarchitecture configurations, power/timing characteristics, training efficacy, and application-level prediction accuracy.
|Effective start/end date||9/1/21 → 8/31/25|
- National Science Foundation (CCF-2106964-001 & 002)