The work involves the characterization and remediation of problems (such as “SLR-crossings”) that would otherwise prevent scaling of trigger algorithms on the Xilinx Ultrascale+ FPGAs used in the Phase-2 L1T upgrade project.
|Effective start/end date||10/1/19 → 12/31/20|
- Fermi Research Alliance, LLC, Fermi National Accelerator Laboratory (NO. 670473//DE-AC02-07CH11359)
- Department of Energy (NO. 670473//DE-AC02-07CH11359)
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