Participant Support Costs (REU) for SHF: Small: Development of Differentiable Memory Augmented Neural CPU Architecture for Cognitive Computing #SP0058979

Project: Research project

Project Details


The development of deep learning techniques has created a new era of computer intelligence. While deep learning can perform well in many supervised classification tasks, the computer is still far behind in term of cognitive behavior that is common to human beings. As a result, much more powerful learning mechanism beyond deep neural networks (DNN) are being actively pursued to bring advanced intelligence into modern computers. Unfortunately, the hardware developments cannot keep up with the fast pace of machine learning (ML) community. The efficiency of the existing hardware is still a limiting factor to support advanced machine learning algorithms on low power devices. Such a deficiency and slowness in hardware adoption is calling for new computer hardware architecture that can be both programmable as a CPU and also power and cost efficient as an ASIC accelerator to support newly derived ML algorithms. In this proposal, we explore a new hardware architecture, regarding as neural CPU, which utilizes neural network to emulate conventional CPU operation leading to a single architecture that maintains the benefits of both architecture. Furthermore, the proposed neural CPU will be extended into more recently developed neural Turing machine or memory augmented neural network to deliver cognitive intelligence to the computer system. Different from conventional CPU or accelerator, the neural CPU is differentiable leading to learning capability to cognitive operations. The large memory access capability of the neural CPU provides strong support to many emerging AI tasks such as life-long learning, meta learning, logic induction, natural language processing, etc. rending a new class of trainable cognitive hardware processor. Through an integrated cross-layer efforts from circuit, CAD, to architecture and compiler, multiple test chips will be built as demonstrations of the new architectures.
Effective start/end date10/1/209/30/23


  • National Science Foundation (CCF-2008906-001)


Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.