Participant Support Costs Supplement for: "SHF: Small: Greybox Computing: An Associative Computing Methodology with Instruction Directed Power and Clock Management"

Project: Research project

Description

Greybox Computing: An Associative Computing Methodology with Instruction Directed Power and Clock Management
Project Summary:
Energy consumption has become the bottleneck for several fastest growing applications such as wearable electronics, biomedical devices. Through more than a decade of improvement, the conventional low power design approaches have reached its maximum achievement bounded by the fundamental tradeoff of performance and power. As a result, new design paradigm needs to be established to continue the journey of energy saving. Conventionally, the hardware and software design are performed separately and treats each other as blackboxes. Different from traditional design approaches, this project aims at creating a “greybox” methodology where the information from hardware design of a microprocessor are visible to the higher level software compilers and vice versa. The additional information from different layers of design space can be used to establish a real-time power optimization operation. Our preliminary analysis shows that by breaking the boundary of traditional design space, significant energy saving that is not obtainable from conventional scheme can be achieved. To efficiently create an associative operation across the boundary of hardware and software, this project will jointly develop several key techniques such as cross mapping between instruction and hardware performance, enhanced power and clock management circuitry for instruction driven operation, calibration based software and hardware optimization. The associative computing methodology proposed in this project can significantly extend the power saving limitation of existing low power technology and provide a new design paradigm on hardware and software optimization.
Intellectual Merit Summary:
The proposed research creates a new systematic cross-layer design methodology that breaks the boundary of conventional design space. The proposed project will yield several key techniques and innovations: (1) based on extensive data study, a new system analysis methodology will be delivered to create effective mapping between software and hardware; (2) Several novel hardware circuitry such as power and clock circuitry, calibration circuits, will be designed to enable the proposed associative operation; (3) A novel instruction driven calibration scheme will be developed to effectively manage the impact of process variation on the microprocessor; (4) A new design optimization methodology will be established to enable bi-directional optimization from software and hardware.
Broader Impacts Summary:
The impacts of the proposed project goes beyond technology improvement. First of all, it promotes a new design environment where software developer and hardware designer work closely to deliver a fully optimized design. Secondly, it fosters mutual training and learning across disciplines in computer engineering in the new era of data driven computing. Students or engineers who work on the proposed approach will become much more productive and valuable for modern developments with data oriented design. We plan to incorporate the learning, finding and execution of the proposed project into our existing computer architecture, VLSI and compiler related classes for students to develop a thorough understanding of the multi-disciplinary aspects of the modern computer design.
StatusActive
Effective start/end date7/1/166/30/20

Funding

  • National Science Foundation (CCF-1618065-001)

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Clocks
Hardware
Costs
Calibration
Microprocessor chips
Energy conservation
Students
Computer architecture
Software design
Energy utilization
Innovation
Systems analysis
Engineers
Networks (circuits)