My proposed activity as a visiting scholar involves analysis and evaluation of custom integrated circuits designed at Fermilab as part of High Energy Physics (HEP) experimental instrumentation. Specifically, I will focus on the power dissipation and thermal behavior of chips that are currently being developed for the next generation data processing units that will be deployed for collider experiments. These experiments generate data on particle trajectories, which need to be recognized subject to their similarity to a known pattern and then fully reconstructed. Among a massive amount of events identified by the detectors within the collider, a subset of tracks that correspond to true events of interest need to be identified in real-time for retention while other background events need to be filtered out efficiently. These experimental systems produce terabytes of data per second and this deluge of data needs to be processed in real time with nanosecond latency per track. This requires a massively parallel computation platform. Researchers at Fermilab have already demonstrated that such a computation platform cannot be constructed with off-the-shelf software programmable processor-based components. In order to meet this agrresive performance target, an effort is underway at the Fermilab to create the next generation custom computing platform to perform hardware based pattern recognition for fast triggering of particle tracks. This effort involves two stages of design and implementation of a pattern recognition architecture as an integrated circuit (IC). When dealing with the design and development of next generation high performance ICs, one of the foremost factors deciding the upper limit of achievable performance is the Thermal Design Point (TDP) metric of the chip. TDP represents the maximum amount of power that can be sustained by the system during reasonably long execution intervals representative of typical workloads, while only short-lived (in the order of microsecond) crossing over this threshold may be allowed. A careful analysis of an IC for its power dissipation and resulting heat generation under expected workloads is therefore a must in design and production of all high performance, densely packaged chips. The custom chip designed at Fermilab to be deployed for the track triggering is no exception to this. My proposed activity will be specifically addressing this important need to achieve design closure for this hardware component under development.
|Effective start/end date||7/1/14 → 6/30/15|
- Universities Research Association, Inc. (14-S-35)
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