RAISE-­EQuiP: Single-­Chip, Wall-­Plug Photon Pair Source and CMOS Quantum Systems on Chip

Proposed Concept: Our vision is to develop silicon quantum electronic-­photonic systems-­on-­chip (QSoCs) that will be enablers of quantum communications networks between quantum nodes (which may become available commercially on a 3-­5 year timeframe). Such networks can allow the scaling of quantum processing power in a way similar to the parallelism of interconnected cores or servers in classical data centers and supercomputers. QSoCs will contain linear and nonlinear optical functions, as well as the required low and high speed electronics needed to implement a high level quantum “function” on a single chip. This allows sophisticated integrated feedback control, scalability/manufacturability (CMOS), high performance photonics [1], and building blocks that will be reusable in design (as a “quantum electronic-­photonic IP library”) in a similar way as electronic circuit blocks are currently reused hierarchically in chip design to enable more complex systems. We propose to demonstrate a “wall plug” single-­chip all-­integrated source of photon pairs – a fundamental building block of most quantum photonic systems, with a high efficiency and rate (target 1MHz after all filtering) and reconfigurable factorizable state (allowing heralding). No such device exists despite the fact that a rack-­mounted fiber-­nonlinearity-­based source of this kind for lab use has been commercialized for almost a decade [2]. We aim in the proposed project to change this quantum technology landscape and demonstrate a fully integrated single-­ chip quantum transmitter system. The on-­chip photonic circuit will contain pre-­ and post-­source linear pump filtering, a resonant nonlinear spontaneous four-­wave-­mixing (SFWM) photon-­pair source, a pump pulse carver to allow active matching of the pump pulse duration to the source’s bandwidth to control the joint spectral intensity (for a factorizable or other engineered biphoton state), and ultra-­low loss interfaces to fiber. We address a number of challenges that arise in integration, on-­chip filtering, and quantum-­state control. In addition to standalone operation, the pair source will be a key building block for more complex integrated systems (e.g., heralded, multiplexed architectures for deterministic single-­photon or qubit/quantum state sources, quantum serializers-­deserializers for time-­encoding of qubits before exit to fiber). Proposed QSoCs will be implemented in a commercial 45nm CMOS electronic-­photonic platform [1] (with potential for single photon detector integration). Team and Vision: We have formed an interdisciplinary team that brings together field-­leading capabilities in: silicon photonic device design and implementation, including quantum photonics (Popović);; CMOS integrated systems and electronics-­photonics integration (Stojanović);; and quantum optical device and system design and experiment (Kumar). Popović and Stojanović demonstrated the first microprocessor with photonic I/O [1], and spun off this research into startup company Ayar Labs. Kumar demonstrated many firsts in quantum communication systems, including inventing the SFWM pair source, quantum frequency conversion, all-­optical quantum switching, implementing quantum games, and founded NuCrypt [2]. We plan to guide the project by a vision of tailored initial quantum system applications based on the team’s experience, such as quantum games, that can provide a useful fieldable application of the proposed QSoC in a near-­term timeframe. Comparison to State of the Art: Previous work on pair gener