SaTC: CORE: Small: Efficient Logic Encryptions for Hardware IP Protection

Project: Research project

Project Details


Hardware is the foundation of all information processing and computational technology. With the increasing deployment of Internet-of-Things (IoT) and mobile and wearable devices, hardware security has become as important (if not more) as general cyber-security. In this project, we are focusing on hardware Intellectual Property (IP) protection, one of the most important hardware security necessity. The hardware IP protection problem is important, not only because the US semiconductor and electronics industry has become more and more fabless and manufacturing-outsourcing, but also due to the fact that IP protection can benefit many other security needs, such as Trojan insertion prevention, side-channel security, and information integrity. The goal of the project is to develop a universal theory and many efficient implementation circuit techniques for hardware IP protection. Existing technologies include logic encryption (also called logic locking or logic obfuscation), circuit camouflaging, split-manufacturing, etc. Without a theoretical foundation, the state-of-the-art and recent research history are filled with repeated cat-and-mouse chases of alternating attacks and defenses. It has happened often that a claimed “provably secure” solution was soon successfully attacked by a slightly different method. Our project strives to change this dilemma by building a solid theoretical foundation for hardware IP protection based on cryptography and theoretical computer science. Based on the universal theory, a substantial amount of efforts in the project will be spent on developing efficient and practical circuit implementation techniques for IP protection. Logic encryption algorithms, circuit design automation tools, and benchmarks will be developed, demonstrated, and released for public use from the project. Treated as implementation techniques of the general theory, circuit-camouflaging and split-manufacturing algorithms and tools will also be developed. Keywords: Hardware Security Design; Hardware Security Architecture Intellectual Merit: The project will start with the investigation of attack models in IP protection that are as broad and general as possible. It will leverage years’ experiences of the PI’s group on many different attacks on logic encryption, including Double DIP, CycSAT, flipping attack, SigAttack, etc. We plan to define a general attack model that subsumes all existing attack methods and beyond, and based on it, define a universal hardware IP protection problem that is secure against the general attack model. The investigation on IP protection techniques will start with a general design for logic encryption that is based on the concept of universal circuits. Our preliminary efforts have established the provable security of the general design under the powerful general attack model. Even though the general design can be thought of as theoretically efficient with a symptomatic O(n logn) size, the project’s goal is to spend efforts to find practically efficient implementations based on quasi-universal circuits. We will also investigate the key protection in circuit techniques, which will naturally place circuit-camouflaging and split-manufacturing into our investigation. Broader Impacts: With the explosion of information and intelligence processing technologies in every aspect of our lives (either private, personal, social, or economic), information security has become a critical part of national and social security. The proposed research will produce techniques to improve hardware securit
Effective start/end date7/1/216/30/25


  • National Science Foundation (CNS 2113704)


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