The processor industry has fallen well short of the decades-old sequential code performance growth trend. Even worst, Moore's law is ending leaving only performance improvements coming from innovations in the microprocessor architecture and the software stack. An important performance roadblock for sequential code running on current commodity processors exist in the sub-cycle domain: the CPU clock period is set to contain all possible latency variations of the circuit-level critical paths. Over the last decade, compiler and architecture researchers have made steady progress toward the goal of effectively reducing the impact of several type of sub-cycle latency variations. However, circuit-level critical path latency variations created by having different data flowing through the processor pipeline has not been properly studied. This left it to be the current dominant source of inefficiency in the commodity hardware/software stack for the whole computing spectrum, from mobile to high performance computing. The goal of this proposed work is to develop techniques to control and limit these data dependent, circuit-level critical path latency variations. The solution requires breaking conventional abstractions between compilers and the underlying computer architecture. The proposed research introduces novel static and dynamic compiler code analyses and transformations tailored to the specifics of the targeted problem, the design of a novel compiler-architecture interaction to efficiently enable the system to find the right balance between architecture-compiler communication overhead and effectiveness of the code transformations, and novel architecture supports for the the specifics of the targeted problem. Keywords: Compiler-architecture co-design; code analysis and transformation, circuit-level critical paths
|Effective start/end date||10/1/19 → 9/30/23|
- National Science Foundation (CCF‐1908488)
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