Chip-scale optical interconnects have been drawing increasing attention in recent years, as the ever-increasing density and performance of electronic circuits has unavoidably come to face the intrinsic limitations of electrical interconnections. However, the current approaches for integrated optical interconnects still fail to meet the requirements in footprint and power consumption that are needed for surpassing the performance of existing electrical interconnects. Arguably, the most important requirement set on optical interconnects is that of low energy consumption, which has been set to below 10 fJ/bit. For the case of the receivers, this results in stringent constraint on the detector sensitivity, capacitance and the driving voltage. Furthermore, a serious challenge is posed by the integration of the two platforms, electronic and photonic, which differ in material systems, functionalities and requirements. The current approaches for integration of III-V optical elements on CMOS platforms include die-to-die and die-to-wafer bonding methods, but all suffer from extremely stringent alignment requirements, which ultimately hinder the performance of the integrated elements and the yield of the process. We propose a novel receiver for optical interconnects that can address these two major shortcomings and achieve integrated receivers with the energy efficiency of less than 10 fJ/Bit with an integration method that can integrate other III-V optoelectronics on almost all silicon CMOS platforms.
|Effective start/end date||8/3/18 → 11/2/21|
- Army Research Office (W911NF1810429 P00006)
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