VeriGOOD-ML: Verilog Generator (Open-source), Optimized for Designs for Machine Learning

Project: Research project

Project Details


In this collaborative project for DARPA, we plan to demonstrate a design automation flow of creating machine learning accelerators for real time machine learning applications. We will create methodology and tools that automatically generate required design files such as verilog RTL codes leading to final GDS for chip fabrication of machine learning accelerators. As part of collaboration, the team in Northwestern University will contribute towards chip implementation including backend layout generation, memory access, clock design as well as chip testing support.
Effective start/end date12/30/191/1/23


  • University of Minnesota (A008043202//FA8650-20-2-7009 Amd No. 4)
  • Air Force Research Laboratory (A008043202//FA8650-20-2-7009 Amd No. 4)


Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.