TY - GEN
T1 - 19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput
AU - Chen, Zhengyu
AU - Gu, Jie
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/3/6
Y1 - 2019/3/6
N2 - Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW a popular method for time-series classification in broad applications, such as ECG diagnosis, motion detection, DNA sequencing, etc. [1]. Several efforts have proposed for accelerating the operation of DTW, including a recent demonstration of time-based design in DNA sequencing [2]. However, the demonstration was confined to single-bit operations, a fixed sequence length and low throughput due to nonpipelined operation and a large single-bit delay. To overcome such challenges, this work presents a general-purpose DTW engine for time-series classification using time-domain computing. Pipelined operation is enabled by a time flip-flop (TFF) leading to order-of-magnitude improvements in throughput and a scalable processing capability for time series. Compared with recent time-domain designs, which do not have time-domain memory elements, this work realizes a time-domain pipelined architecture [3].
AB - Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW a popular method for time-series classification in broad applications, such as ECG diagnosis, motion detection, DNA sequencing, etc. [1]. Several efforts have proposed for accelerating the operation of DTW, including a recent demonstration of time-based design in DNA sequencing [2]. However, the demonstration was confined to single-bit operations, a fixed sequence length and low throughput due to nonpipelined operation and a large single-bit delay. To overcome such challenges, this work presents a general-purpose DTW engine for time-series classification using time-domain computing. Pipelined operation is enabled by a time flip-flop (TFF) leading to order-of-magnitude improvements in throughput and a scalable processing capability for time series. Compared with recent time-domain designs, which do not have time-domain memory elements, this work realizes a time-domain pipelined architecture [3].
UR - http://www.scopus.com/inward/record.url?scp=85063468916&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063468916&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2019.8662340
DO - 10.1109/ISSCC.2019.8662340
M3 - Conference contribution
AN - SCOPUS:85063468916
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 324
EP - 326
BT - 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Y2 - 17 February 2019 through 21 February 2019
ER -