6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC across 80MHz BW and >15dBm TX Power-Handling

Aravind Nagulu, Sasank Garikapati, Mostafa Essawy, Igor Kadota, Tingjun Chen, Arun Natarajan, Gil Zussman, Harish Krishnaswamy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Full-duplex (FD) transceivers remain a significant challenge as they require \gt 100 dB of cancellation of high levels of self-interference (SI), recreation of large SI channel delay spreads, and real-time canceler adaptation. SI cancelers based on frequency-domain equalization (FDE) [1], [2] demand multiple widely-tunable power-hungry high-Q filters, while those based on FIR-based time-domain equalization (TDE) [3] -[5] require large delays with fine resolution (see Fig. 6.6.1 for a system simulation based on the isolation profile of an SI channel, where the TX-RX leakage spreads across several 10s of nanoseconds). Additionally, supporting realistic antenna interface isolations of \sim20 dB requires a low-loss canceler and stresses canceler noise and linearity [6]. This work introduces - (i) an N-path switched-capacitor (SC) delay-line with stacked-capacitor voltage gain while enabling nearly ten nanoseconds of RF true-time delay across a large BW (DC to 1GHz), (ii) a new LNTA canceler where the FIR weighting, summation, and output buffer of the canceler is absorbed into the LNTA, and (iii) a closed-loop adaptation algorithm leveraging analytical modeling of tap non-idealities that reduces the computational complexity and data storage. Leveraging a 16-tap RF canceler operating across DC to 1GHz with delays ranging from 0.25ps to 8ns (8 \times compared to [5] and 40 \times compared to [4]) and a complex-weighted 8-tap BB canceler with delays ranging from 10ns to 85ns, the FD receiver achieves (i) tunable operation across 200MHz to 1GHz, (ii) wideband SI suppression of up to 65dB (54dB) across 40MHz (80MHz), when operating at 800MHz (13dB higher than [5] while achieving 2 \times cancellation BW), with (iii) modest NF degradation of 0.8dB (2.8dB) for the low-power mode (high-power mode), while (iv) handling TX power of up to +15 dBm (6dB higher than [5]) across an initial circulator isolation of only 23dB (11 to 18dB better than [1] -[4]).

Original languageEnglish (US)
Title of host publication2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages100-102
Number of pages3
ISBN (Electronic)9781728195490
DOIs
StatePublished - Feb 13 2021
Event2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States
Duration: Feb 13 2021Feb 22 2021

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume64
ISSN (Print)0193-6530

Conference

Conference2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Country/TerritoryUnited States
CitySan Francisco
Period2/13/212/22/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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