TY - GEN
T1 - 6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC across 80MHz BW and >15dBm TX Power-Handling
AU - Nagulu, Aravind
AU - Garikapati, Sasank
AU - Essawy, Mostafa
AU - Kadota, Igor
AU - Chen, Tingjun
AU - Natarajan, Arun
AU - Zussman, Gil
AU - Krishnaswamy, Harish
N1 - Funding Information:
This work was supported by DARPA SPAR, SRC-DARPA ComSenTer center, and NSF grant ECCS-1547406.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/2/13
Y1 - 2021/2/13
N2 - Full-duplex (FD) transceivers remain a significant challenge as they require \gt 100 dB of cancellation of high levels of self-interference (SI), recreation of large SI channel delay spreads, and real-time canceler adaptation. SI cancelers based on frequency-domain equalization (FDE) [1], [2] demand multiple widely-tunable power-hungry high-Q filters, while those based on FIR-based time-domain equalization (TDE) [3] -[5] require large delays with fine resolution (see Fig. 6.6.1 for a system simulation based on the isolation profile of an SI channel, where the TX-RX leakage spreads across several 10s of nanoseconds). Additionally, supporting realistic antenna interface isolations of \sim20 dB requires a low-loss canceler and stresses canceler noise and linearity [6]. This work introduces - (i) an N-path switched-capacitor (SC) delay-line with stacked-capacitor voltage gain while enabling nearly ten nanoseconds of RF true-time delay across a large BW (DC to 1GHz), (ii) a new LNTA canceler where the FIR weighting, summation, and output buffer of the canceler is absorbed into the LNTA, and (iii) a closed-loop adaptation algorithm leveraging analytical modeling of tap non-idealities that reduces the computational complexity and data storage. Leveraging a 16-tap RF canceler operating across DC to 1GHz with delays ranging from 0.25ps to 8ns (8 \times compared to [5] and 40 \times compared to [4]) and a complex-weighted 8-tap BB canceler with delays ranging from 10ns to 85ns, the FD receiver achieves (i) tunable operation across 200MHz to 1GHz, (ii) wideband SI suppression of up to 65dB (54dB) across 40MHz (80MHz), when operating at 800MHz (13dB higher than [5] while achieving 2 \times cancellation BW), with (iii) modest NF degradation of 0.8dB (2.8dB) for the low-power mode (high-power mode), while (iv) handling TX power of up to +15 dBm (6dB higher than [5]) across an initial circulator isolation of only 23dB (11 to 18dB better than [1] -[4]).
AB - Full-duplex (FD) transceivers remain a significant challenge as they require \gt 100 dB of cancellation of high levels of self-interference (SI), recreation of large SI channel delay spreads, and real-time canceler adaptation. SI cancelers based on frequency-domain equalization (FDE) [1], [2] demand multiple widely-tunable power-hungry high-Q filters, while those based on FIR-based time-domain equalization (TDE) [3] -[5] require large delays with fine resolution (see Fig. 6.6.1 for a system simulation based on the isolation profile of an SI channel, where the TX-RX leakage spreads across several 10s of nanoseconds). Additionally, supporting realistic antenna interface isolations of \sim20 dB requires a low-loss canceler and stresses canceler noise and linearity [6]. This work introduces - (i) an N-path switched-capacitor (SC) delay-line with stacked-capacitor voltage gain while enabling nearly ten nanoseconds of RF true-time delay across a large BW (DC to 1GHz), (ii) a new LNTA canceler where the FIR weighting, summation, and output buffer of the canceler is absorbed into the LNTA, and (iii) a closed-loop adaptation algorithm leveraging analytical modeling of tap non-idealities that reduces the computational complexity and data storage. Leveraging a 16-tap RF canceler operating across DC to 1GHz with delays ranging from 0.25ps to 8ns (8 \times compared to [5] and 40 \times compared to [4]) and a complex-weighted 8-tap BB canceler with delays ranging from 10ns to 85ns, the FD receiver achieves (i) tunable operation across 200MHz to 1GHz, (ii) wideband SI suppression of up to 65dB (54dB) across 40MHz (80MHz), when operating at 800MHz (13dB higher than [5] while achieving 2 \times cancellation BW), with (iii) modest NF degradation of 0.8dB (2.8dB) for the low-power mode (high-power mode), while (iv) handling TX power of up to +15 dBm (6dB higher than [5]) across an initial circulator isolation of only 23dB (11 to 18dB better than [1] -[4]).
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U2 - 10.1109/ISSCC42613.2021.9365947
DO - 10.1109/ISSCC42613.2021.9365947
M3 - Conference contribution
AN - SCOPUS:85102373243
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 100
EP - 102
BT - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Y2 - 13 February 2021 through 22 February 2021
ER -