TY - JOUR
T1 - A 28 nm 0.6 v low power DSP for mobile applications
AU - Ickes, Nathan
AU - Gammie, Gordon
AU - Sinangil, Mahmut E.
AU - Rithe, Rahul
AU - Gu, Jie
AU - Wang, Alice
AU - Mair, Hugh
AU - Datla, Satyendra
AU - Rong, Bing
AU - Honnavara-Prasad, Sushma
AU - Ho, Lam
AU - Baldwin, Greg
AU - Buss, Dennis
AU - Chandrakasan, Anantha P.
AU - Ko, Uming
PY - 2012/1
Y1 - 2012/1
N2 - Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (V T) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local V T variation and achieve a reliable design with minimal pessimism.
AB - Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (V T) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local V T variation and achieve a reliable design with minimal pessimism.
KW - Low power electronics
KW - microprocessors
UR - http://www.scopus.com/inward/record.url?scp=84655166926&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84655166926&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2011.2169689
DO - 10.1109/JSSC.2011.2169689
M3 - Article
AN - SCOPUS:84655166926
SN - 0018-9200
VL - 47
SP - 35
EP - 46
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 1
M1 - 6081953
ER -