A 28nm 0.6V low-power DSP for mobile applications

Gordon Gammie*, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, J. Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara-Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32-register version of the TMS320C64x+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM. Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methodology, the SoC scales as designed from high performance at 1.0V down to ultra-low power at 0.6V.

Original languageEnglish (US)
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages132-133
Number of pages2
DOIs
StatePublished - 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: Feb 20 2011Feb 24 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/TerritoryUnited States
CitySan Francisco, CA
Period2/20/112/24/11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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