TY - GEN
T1 - A 28nm 0.6V low-power DSP for mobile applications
AU - Gammie, Gordon
AU - Ickes, Nathan
AU - Sinangil, Mahmut E.
AU - Rithe, Rahul
AU - Gu, J.
AU - Wang, Alice
AU - Mair, Hugh
AU - Datla, Satyendra
AU - Rong, Bing
AU - Honnavara-Prasad, Sushma
AU - Ho, Lam
AU - Baldwin, Greg
AU - Buss, Dennis
AU - Chandrakasan, Anantha P.
AU - Ko, Uming
PY - 2011
Y1 - 2011
N2 - A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32-register version of the TMS320C64x+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM. Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methodology, the SoC scales as designed from high performance at 1.0V down to ultra-low power at 0.6V.
AB - A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32-register version of the TMS320C64x+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM. Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methodology, the SoC scales as designed from high performance at 1.0V down to ultra-low power at 0.6V.
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U2 - 10.1109/ISSCC.2011.5746251
DO - 10.1109/ISSCC.2011.5746251
M3 - Conference contribution
AN - SCOPUS:79955707786
SN - 9781612843001
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 132
EP - 133
BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Y2 - 20 February 2011 through 24 February 2011
ER -