TY - JOUR
T1 - A 65-nm ReRAM-Enabled Nonvolatile Processor with Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4× Faster Clock Frequency and $> 6× Higher Restore Speed
AU - Wang, Zhibo
AU - Liu, Yongpan
AU - Lee, Albert
AU - Su, Fang
AU - Lo, Chieh Pu
AU - Yuan, Zhe
AU - Li, Jinyang
AU - Lin, Chien Chen
AU - Chen, Wei Hao
AU - Chiu, Hsiao Yun
AU - Lin, Wei En
AU - King, Ya Chin
AU - Lin, Chrong Jung
AU - Khalili Amiri, Pedram
AU - Wang, Kang Lung
AU - Chang, Meng Fan
AU - Yang, Huazhong
N1 - Funding Information:
Manuscript received February 2, 2017; revised June 3, 2017; accepted June 26, 2017. Date of publication August 7, 2017; date of current version September 21, 2017. This paper was approved by Associate Editor Vivek De. This work was supported in part by NSFC under Grant 61674094 and in part by the Beijing Innovation Center for Future Chip. (Corresponding author: Yongpan Liu.) Z. Wang, Y. Liu, F. Su, Z. Yuan, J. Li, and H. Yang are with Tsinghua University, Beijing 10084, China (e-mail: [email protected]). A. Lee is with National Tsing Hua University, Hsinchu 30013, Taiwan, and also with the University of California, Los Angeles, CA 90095 USA. C.-P. Lo, C.-C. Lin, W.-H. Chen, H.-Y. Chiu, W.-E. Lin, Y.-C. King, C.-J. Lin, and M.-F. Chang are with the National Tsing Hua University, Hsinchu 30013, Taiwan. P. Khalili Amiri and K.-L. Wang are with the University of California, Los Angeles, CA 90095 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2017.2724024
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10
Y1 - 2017/10
N2 - With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as 'normally off' applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6 × and >6000 × higher speed and energy efficiency of restore and >4 × faster operating frequency compared with that of state of the art.
AB - With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as 'normally off' applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6 × and >6000 × higher speed and energy efficiency of restore and >4 × faster operating frequency compared with that of state of the art.
KW - Nonvolatile processor (NVP)
KW - nonvolatile SRAM (nvSRAM)
KW - nonvolatile flip-flops (nvFF)
KW - self-write termination (SWT)
KW - time-space domain adaption
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U2 - 10.1109/JSSC.2017.2724024
DO - 10.1109/JSSC.2017.2724024
M3 - Article
AN - SCOPUS:85028947486
SN - 0018-9200
VL - 52
SP - 2769
EP - 2785
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 10
M1 - 8003272
ER -
