A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh Pu Lo, Zhe Yuan, Chien Chen Lin, Qi Wei, Yu Wang, Ya Chin King, Chrong Jung Lin, Pedram Khalili, Kang Lung Wang, Meng Fan Chang, Huazhong Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

71 Scopus citations

Abstract

With the rising importance of energy efficiency, zero leakage power and instant-on capability are highly desired features in energy harvesting sensors, as well as normally off high performance processors. However, intermittent power in such systems requires nonvolatile memory (NVM) to hold intermediate data and avoid rollbacks. Previous work has adopted FeRAM and STT-MRAM to achieve zero-standby power and fast-restore nonvolatile processors (NVPs) [1-3]. Previous NVPs, however, suffer from several drawbacks: 1) Various power interrupt periods are not considered; 2) the 2-macro memory architecture slows access speed; 3) worst-case store/restore operations are always performed. We present a 65nm fully-CMOS-logic-compatible ReRAM-based NVP achieving time/space-adaptive data retention. A 1-macro nvSRAM with self-write-termination (SWT) is integrated to boost clock frequency and reduce store energy. The adaptive retention and SWT strategy relieve the ReRAM write endurance challenge (106-1012), making it sufficient for most applications. The NVP operates at 100MHz with 20ns/0.45nJ restore time (TRESTORE)/energy (ERESTORE), realizing 6× reduction in TRESTORE, >6000× reduction in ERESTORE and 4× higher clock frequency compared with existing designs.

Original languageEnglish (US)
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages84-86
Number of pages3
ISBN (Electronic)9781467394666
DOIs
StatePublished - Feb 23 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: Jan 31 2016Feb 4 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume59
ISSN (Print)0193-6530

Other

Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period1/31/162/4/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic'. Together they form a unique fingerprint.

  • Cite this

    Liu, Y., Wang, Z., Lee, A., Su, F., Lo, C. P., Yuan, Z., Lin, C. C., Wei, Q., Wang, Y., King, Y. C., Lin, C. J., Khalili, P., Wang, K. L., Chang, M. F., & Yang, H. (2016). A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016 (pp. 84-86). [7417918] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 59). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2016.7417918