A C to hardware/software compiler

Kiarash Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


Improvements in the FPGA technology have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. This paper presents a top-down compilation method, under development, for such systems. We compile a C program into hierarchical VHDL source files, and annotate them with the placement information of the hardware modules to be configured on the FPGA. Static scheduling combined with a fast, two-stage placement core reduces the compilation time of large programs to minutes.

Original languageEnglish (US)
Title of host publicationProceedings - 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
EditorsBrad L. Hutchings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)0769508715
StatePublished - 2000
EventIEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2000 - Napa Valley, United States
Duration: Apr 17 2000Apr 19 2000

Publication series

NameIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
ISSN (Print)1082-3409


OtherIEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2000
Country/TerritoryUnited States
CityNapa Valley

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Theoretical Computer Science


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