TY - GEN

T1 - A combined decimal and binary floating-point multiplier

AU - Tsen, Charles

AU - González-Navarro, Sonia

AU - Schulte, Michael

AU - Hickmann, Brian

AU - Compton, Katherine

N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.

PY - 2009

Y1 - 2009

N2 - In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 Floating-point Standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58% of the total area required by separate BFP and DFP units. Furthermore, the critical path delay of the combined multiplier has a negligible increase over that of a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

AB - In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 Floating-point Standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58% of the total area required by separate BFP and DFP units. Furthermore, the critical path delay of the combined multiplier has a negligible increase over that of a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

KW - Binary integer decimal

KW - Commercial applications

KW - Computer arithmetic

KW - Decimal

KW - Floating-point

KW - Hardware

KW - Hardware reuse

KW - IEEE 754-2008

KW - Multiplication

KW - Register-transfer-level implementation

UR - http://www.scopus.com/inward/record.url?scp=71049116424&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71049116424&partnerID=8YFLogxK

U2 - 10.1109/ASAP.2009.28

DO - 10.1109/ASAP.2009.28

M3 - Conference contribution

AN - SCOPUS:71049116424

SN - 9780769537320

T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

SP - 8

EP - 15

BT - Proceedings - 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009

T2 - 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009

Y2 - 7 July 2009 through 9 July 2009

ER -