A combined decimal and binary floating-point multiplier

Charles Tsen*, Sonia González-Navarro, Michael Schulte, Brian Hickmann, Katherine Compton

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 Floating-point Standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58% of the total area required by separate BFP and DFP units. Furthermore, the critical path delay of the combined multiplier has a negligible increase over that of a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009
Pages8-15
Number of pages8
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009 - Boston, MA, United States
Duration: Jul 7 2009Jul 9 2009

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Conference

Conference2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009
CountryUnited States
CityBoston, MA
Period7/7/097/9/09

Keywords

  • Binary integer decimal
  • Commercial applications
  • Computer arithmetic
  • Decimal
  • Floating-point
  • Hardware
  • Hardware reuse
  • IEEE 754-2008
  • Multiplication
  • Register-transfer-level implementation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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