TY - GEN
T1 - A Comprehensive Tapered buffer optimization algorithm for unified design metrics
AU - Liu, Song
AU - Ogrenci Memik, Seda
AU - Ismail, Yehea I.
PY - 2011
Y1 - 2011
N2 - Tapered buffers are widely used in CMOS integrated circuits to drive large capacitive loads. During the design of a tapered buffer, there are several design objectives to consider including delay, area, and power consumption. Existing methods produce suboptimal solutions considering multiple metrics, largely because they decouple different metrics during the design phase, which restricts the solution space for the combined metric. In this paper, a new algorithm is proposed to derive the optimal solution for a unified metric through comprehensive exploration of the solution space. Compared with existing methods, our method yields as high as 18.8% (9.0% on average) improvement in a unified design metric optimizing area, delay, and power simultaneously. The proposed algorithm also reduces buffer power consumption under delay constraints. The power reduction over existing alternatives is as much as 48.1% (28.7% on average).
AB - Tapered buffers are widely used in CMOS integrated circuits to drive large capacitive loads. During the design of a tapered buffer, there are several design objectives to consider including delay, area, and power consumption. Existing methods produce suboptimal solutions considering multiple metrics, largely because they decouple different metrics during the design phase, which restricts the solution space for the combined metric. In this paper, a new algorithm is proposed to derive the optimal solution for a unified metric through comprehensive exploration of the solution space. Compared with existing methods, our method yields as high as 18.8% (9.0% on average) improvement in a unified design metric optimizing area, delay, and power simultaneously. The proposed algorithm also reduces buffer power consumption under delay constraints. The power reduction over existing alternatives is as much as 48.1% (28.7% on average).
UR - http://www.scopus.com/inward/record.url?scp=79960869738&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79960869738&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2011.5938056
DO - 10.1109/ISCAS.2011.5938056
M3 - Conference contribution
AN - SCOPUS:79960869738
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2277
EP - 2280
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -