A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators

Tianyu Jia, Yuhao Ju, Jie Gu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic timing error detection and correction techniques, e.g. razor flops, have been previously applied to microprocessors to exploit the dynamic timing margin within pipelines [1]. Adaptive clock techniques have also been adopted to enhance microprocessor performance, such as schemes to reduce the timing guardband for on-chip supply droops [2]-[3] or to exploit instruction-level dynamic timing slack [4]. Recently, 2D PE array-based accelerators have been developed for machine learning (ML) applications. Many efforts have been dedicated to improve the energy efficiency of such accelerators, e.g. DVFS management for the DNN under various bit precision [5]. A razor technique was also applied to a 1D 8-MAC pipelined accelerator to explore timing error tolerance [6]. Despite the above efforts, a fine-grained dynamic-timing-based technique has not been implemented within a large 2D array based ML accelerator. One main challenge comes from the large amount of compute-timing bottlenecks within the 2D array, which will continuously trigger critical path adaptation or pipeline stalls, nullifying the benefits of previous dynamic-timing techniques [4], [6]. To deal with the difficulty, we propose the following solutions. A local in-situ compute-detection scheme was applied to anticipate upcoming timing variations within the PE unit and guide both instruction-based and operand-based adaptive clock management. To loosen the stringent timing requirements in a large 2D PE array, an 'elastic' clock-chain technique using multiple loosely synchronized clock domains was developed enabling dynamic-timing enhancement through clusters of PE units.

Original languageEnglish (US)
Title of host publication2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages482-484
Number of pages3
ISBN (Electronic)9781728132044
DOIs
StatePublished - Feb 2020
Event2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 - San Francisco, United States
Duration: Feb 16 2020Feb 20 2020

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2020-February
ISSN (Print)0193-6530

Conference

Conference2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
CountryUnited States
CitySan Francisco
Period2/16/202/20/20

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Jia, T., Ju, Y., & Gu, J. (2020). A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 (pp. 482-484). [9063062] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC19947.2020.9063062