@inproceedings{914616244fc148139b466dbd29c45e0f,
title = "A content addressable memory with multi-Vdd scheme for low power tunable operation",
abstract = "This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes 25.3% less power when compared to a conventional single-Vdd design operating over the same voltage range. Measurement results from a 246 kb test chip fabricated in 130nm Global Foundries Low Power CMOS technology are presented to validate the model and analysis.",
keywords = "Associative memory, Content addressable memory (CAM), Low power, Multi Vdd, Multi supply, TCAM, Tunable operation",
author = "Siddhartha Joshi and Dawei Li and Seda Ogrenci-Memik and Grzegorz Deptuch and James Hoff and Sergo Jindariani and Tiehui Liu and Jamieson Olsen and Nhan Tran",
note = "Funding Information: This work was partially supported by the NSF Grant CCF-1422489. Publisher Copyright: {\textcopyright} 2017 IEEE.; 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 ; Conference date: 06-08-2017 Through 09-08-2017",
year = "2017",
month = sep,
day = "27",
doi = "10.1109/MWSCAS.2017.8052945",
language = "English (US)",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "401--404",
booktitle = "2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017",
address = "United States",
}