A content addressable memory with multi-Vdd scheme for low power tunable operation

Siddhartha Joshi, Dawei Li, Seda Ogrenci-Memik, Grzegorz Deptuch, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes 25.3% less power when compared to a conventional single-Vdd design operating over the same voltage range. Measurement results from a 246 kb test chip fabricated in 130nm Global Foundries Low Power CMOS technology are presented to validate the model and analysis.

Original languageEnglish (US)
Title of host publication2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages401-404
Number of pages4
ISBN (Electronic)9781509063895
DOIs
StatePublished - Sep 27 2017
Event60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: Aug 6 2017Aug 9 2017

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2017-August
ISSN (Print)1548-3746

Other

Other60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
CountryUnited States
CityBoston
Period8/6/178/9/17

Fingerprint

Associative storage
Foundries
Pattern recognition
Testing
Electric potential

Keywords

  • Associative memory
  • Content addressable memory (CAM)
  • Low power
  • Multi Vdd
  • Multi supply
  • TCAM
  • Tunable operation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Joshi, S., Li, D., Ogrenci-Memik, S., Deptuch, G., Hoff, J., Jindariani, S., ... Tran, N. (2017). A content addressable memory with multi-Vdd scheme for low power tunable operation. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 (pp. 401-404). [8052945] (Midwest Symposium on Circuits and Systems; Vol. 2017-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2017.8052945
Joshi, Siddhartha ; Li, Dawei ; Ogrenci-Memik, Seda ; Deptuch, Grzegorz ; Hoff, James ; Jindariani, Sergo ; Liu, Tiehui ; Olsen, Jamieson ; Tran, Nhan. / A content addressable memory with multi-Vdd scheme for low power tunable operation. 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 401-404 (Midwest Symposium on Circuits and Systems).
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Joshi, S, Li, D, Ogrenci-Memik, S, Deptuch, G, Hoff, J, Jindariani, S, Liu, T, Olsen, J & Tran, N 2017, A content addressable memory with multi-Vdd scheme for low power tunable operation. in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017., 8052945, Midwest Symposium on Circuits and Systems, vol. 2017-August, Institute of Electrical and Electronics Engineers Inc., pp. 401-404, 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, United States, 8/6/17. https://doi.org/10.1109/MWSCAS.2017.8052945

A content addressable memory with multi-Vdd scheme for low power tunable operation. / Joshi, Siddhartha; Li, Dawei; Ogrenci-Memik, Seda; Deptuch, Grzegorz; Hoff, James; Jindariani, Sergo; Liu, Tiehui; Olsen, Jamieson; Tran, Nhan.

2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 401-404 8052945 (Midwest Symposium on Circuits and Systems; Vol. 2017-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes 25.3% less power when compared to a conventional single-Vdd design operating over the same voltage range. Measurement results from a 246 kb test chip fabricated in 130nm Global Foundries Low Power CMOS technology are presented to validate the model and analysis.

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Joshi S, Li D, Ogrenci-Memik S, Deptuch G, Hoff J, Jindariani S et al. A content addressable memory with multi-Vdd scheme for low power tunable operation. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 401-404. 8052945. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2017.8052945