A Cu interconnect process for the 130 nm process technology node

Peter Moon*, C. Allen, N. Anand, D. Austin, T. Bramblett, M. Fradkin, S. Fu, M. Hussein, J. Jeong, C. Lo, A. Ott, P. Smith, L. Rumaner

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

A Cu interconnect process for the 130 nm logic process technology generation using dual damascene copper interconnects and fluorosilicate glass (FSG) was described. The technology exhibited 30% lower sheet resistances at the same metal pitch due to use of Cu with higher aspect ratios. It achieved minimal erosion due to use of the chemical mechanical polishing (CMP) process, and demonstrated high yield on both 200 nm and 300 nm wafers.

Original languageEnglish (US)
Pages (from-to)39-41
Number of pages3
JournalAdvanced Metallization Conference (AMC)
StatePublished - Dec 1 2001
EventAdvanced Metallization Conference 2001 (AMC 2001) - Montreal, Que., Canada
Duration: Oct 8 2001Oct 11 2001

ASJC Scopus subject areas

  • Chemical Engineering(all)

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