A Cu interconnect process for the 130 nm process technology node

Peter Moon; C. Allen; N. Anand; D. Austin; T. Bramblett; M. Fradkin; S. Fu; M. Hussein; J. Jeong; C. Lo; A. Ott; P. Smith; L. Rumaner

A Cu interconnect process for the 130 nm process technology node

Peter Moon^*, C. Allen, N. Anand, D. Austin, T. Bramblett, M. Fradkin, S. Fu, M. Hussein, J. Jeong, C. Lo, A. Ott, P. Smith, L. Rumaner

^*Corresponding author for this work

Chemistry

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A Cu interconnect process for the 130 nm logic process technology generation using dual damascene copper interconnects and fluorosilicate glass (FSG) was described. The technology exhibited 30% lower sheet resistances at the same metal pitch due to use of Cu with higher aspect ratios. It achieved minimal erosion due to use of the chemical mechanical polishing (CMP) process, and demonstrated high yield on both 200 nm and 300 nm wafers.

Original language	English (US)
Pages (from-to)	39-41
Number of pages	3
Journal	Advanced Metallization Conference (AMC)
State	Published - Dec 1 2001
Event	Advanced Metallization Conference 2001 (AMC 2001) - Montreal, Que., Canada Duration: Oct 8 2001 → Oct 11 2001

ASJC Scopus subject areas

Chemical Engineering(all)

Cite this

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title = "A Cu interconnect process for the 130 nm process technology node",

abstract = "A Cu interconnect process for the 130 nm logic process technology generation using dual damascene copper interconnects and fluorosilicate glass (FSG) was described. The technology exhibited 30% lower sheet resistances at the same metal pitch due to use of Cu with higher aspect ratios. It achieved minimal erosion due to use of the chemical mechanical polishing (CMP) process, and demonstrated high yield on both 200 nm and 300 nm wafers.",

author = "Peter Moon and C. Allen and N. Anand and D. Austin and T. Bramblett and M. Fradkin and S. Fu and M. Hussein and J. Jeong and C. Lo and A. Ott and P. Smith and L. Rumaner",

year = "2001",

month = dec,

day = "1",

language = "English (US)",

pages = "39--41",

journal = "Advanced Metallization Conference (AMC)",

issn = "1048-0854",

note = "Advanced Metallization Conference 2001 (AMC 2001) ; Conference date: 08-10-2001 Through 11-10-2001",

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TY - JOUR

T1 - A Cu interconnect process for the 130 nm process technology node

AU - Moon, Peter

AU - Allen, C.

AU - Anand, N.

AU - Austin, D.

AU - Bramblett, T.

AU - Fradkin, M.

AU - Fu, S.

AU - Hussein, M.

AU - Jeong, J.

AU - Lo, C.

AU - Ott, A.

AU - Smith, P.

AU - Rumaner, L.

PY - 2001/12/1

Y1 - 2001/12/1

N2 - A Cu interconnect process for the 130 nm logic process technology generation using dual damascene copper interconnects and fluorosilicate glass (FSG) was described. The technology exhibited 30% lower sheet resistances at the same metal pitch due to use of Cu with higher aspect ratios. It achieved minimal erosion due to use of the chemical mechanical polishing (CMP) process, and demonstrated high yield on both 200 nm and 300 nm wafers.

AB - A Cu interconnect process for the 130 nm logic process technology generation using dual damascene copper interconnects and fluorosilicate glass (FSG) was described. The technology exhibited 30% lower sheet resistances at the same metal pitch due to use of Cu with higher aspect ratios. It achieved minimal erosion due to use of the chemical mechanical polishing (CMP) process, and demonstrated high yield on both 200 nm and 300 nm wafers.

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UR - http://www.scopus.com/inward/citedby.url?scp=0035554937&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0035554937

SP - 39

EP - 41

JO - Advanced Metallization Conference (AMC)

JF - Advanced Metallization Conference (AMC)

SN - 1048-0854

T2 - Advanced Metallization Conference 2001 (AMC 2001)

Y2 - 8 October 2001 through 11 October 2001

ER -

A Cu interconnect process for the 130 nm process technology node

Abstract

ASJC Scopus subject areas

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