TY - JOUR
T1 - A dual-data line read scheme for high-speed low-energy resistive nonvolatile memories
AU - Lee, Albert
AU - Lee, Hochul
AU - Ebrahimi, Farbod
AU - Lam, Bonnie
AU - Chen, Wei Hao
AU - Chang, Meng Fan
AU - Amiri, Pedram Khalili
AU - Wang, Kang L.
N1 - Funding Information:
Manuscript received June 6, 2017; revised September 8, 2017; accepted October 17, 2017. Date of publication November 14, 2017; date of current version January 19, 2018. This work was supported in part by Inston Inc., in part by CEGN, and in part by DARPA under Contract FA8650-16-7655. (Corresponding author: Albert Lee.) A. Lee is with the Electrical Engineering Department, University of California at Los Angeles, Los Angeles, CA 90095 USA and also with Inston Inc., Los Angeles, CA 90095 USA (e-mail: oncefriends9206@gmail.com).
Publisher Copyright:
© 2017 IEEE.
PY - 2018/2
Y1 - 2018/2
N2 - Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%.
AB - Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%.
KW - Magnetoelectric RAM (MeRAM)
KW - Phase-change memory
KW - Resistive memory
KW - Spin-transfer torque (STT)magnetoresistive random access memory (MRAM)
KW - Voltage-mode sensing
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U2 - 10.1109/TVLSI.2017.2766150
DO - 10.1109/TVLSI.2017.2766150
M3 - Article
AN - SCOPUS:85035135364
VL - 26
SP - 272
EP - 279
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 2
M1 - 2766150
ER -