Abstract
With continuous down-scaling of minimum feature sizes and increasing of chip areas, buffering has become a necessary technique to control the interconnect delays in VLSI chips. Recently, Shi and Li proposed an efficient O(n log n) time algorithm to speed up buffering. Based on balanced binary search trees, their algorithm showed superb performance with the most unbalanced sizes of merging solution lists. We propose in this paper a more flexible data structure for the same buffering operations. With parameters to adjust, our algorithm works better than Shi and Li under all cases: unbalanced, balanced, and mix sizes. Our data structure is also simpler than theirs.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 216-221 |
| Number of pages | 6 |
| Journal | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| State | Published - 2004 |
| Event | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States Duration: Oct 11 2004 → Oct 13 2004 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering