A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida

doi:10.1016/j.vlsi.2012.02.005

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

Alberto A. Del Barrio^*, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

State of the art multi-objective synthesis flows use to degrade some parameters of the circuit while trying to optimize the target one. This paper addresses the power reduction problem in heterogeneous datapaths, while keeping a similar area and execution time with respect to the baseline case. Our specific approach first diminishes the area via fragmentation techniques and afterwards it gives it back with the introduction of Low Power Functional Units (LP-FUs) that occupy more area than their corresponding non-low power counterparts. Furthermore, a fragmentation algorithm more suitable for power reduction is proposed. Results show that it is possible to diminish power by 27% on average (49% in the best case).

Original language	English (US)
Pages (from-to)	119-130
Number of pages	12
Journal	Integration, the VLSI Journal
Volume	46
Issue number	2
DOIs	https://doi.org/10.1016/j.vlsi.2012.02.005
State	Published - Mar 1 2013

Keywords

Area
High-Level Synthesis
Low power

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1016/j.vlsi.2012.02.005

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AU - Hermida, Román

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