A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training

Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, Levi Hargrove

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

An ultra-low-power gesture and gait classification SoC is presented for rehabilitation application featuring (1) mixed-signal feature extraction and integrated low-noise amplifier eliminating expensive ADC and digital feature extraction, (2) an integrated distributed deep neural network (DNN) ASIC supporting a scalable multi-chip neural network for sensor fusion with distortion resiliency for low-cost front end modules, (3) onchip learning of DNN engine allowing in-situ training of user specific operations. A 12-channel 65nm CMOS test chip was fabricated with 1μW power per channel, less than 3ms computation latency, on-chip training for user-specific DNN model and multi-chip networking capability.

Original languageEnglish (US)
Title of host publication2020 IEEE Custom Integrated Circuits Conference, CICC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728160313
DOIs
StatePublished - Mar 2020
Event2020 IEEE Custom Integrated Circuits Conference, CICC 2020 - Boston, United States
Duration: Mar 22 2020Mar 25 2020

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2020-March
ISSN (Print)0886-5930

Conference

Conference2020 IEEE Custom Integrated Circuits Conference, CICC 2020
CountryUnited States
CityBoston
Period3/22/203/25/20

Keywords

  • deep neural network
  • edge processing
  • inter-chip communication
  • mixed-signal feature extraction
  • on-chip learning

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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