A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

Yuhao Ju*, Yijie Wei, Xi Chen, Jie Gu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.

Original languageEnglish (US)
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
StatePublished - 2023
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: Jun 11 2023Jun 16 2023

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period6/11/236/16/23

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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