A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

Yuhao Ju; Yijie Wei; Xi Chen; Jie Gu

doi:10.23919/VLSITechnologyandCir57934.2023.10185311

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

Yuhao Ju^*, Yijie Wei, Xi Chen, Jie Gu

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.

Original language	English (US)
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185311
State	Published - 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: Jun 11 2023 → Jun 16 2023

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	6/11/23 → 6/16/23

Funding

Fig. 8 A detailed case study on the SLAM application from GPCIM. Acknowledgements This work is supported in part by NSF grant CCF-2008906.

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185311

Cite this

Ju, Y., Wei, Y., Chen, X., & Gu, J. (2023). A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185311

Ju, Yuhao ; Wei, Yijie ; Chen, Xi et al. / A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{fee1bad4ff874943bddb9cd95b080ace,

title = "A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality",

abstract = "This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.",

author = "Yuhao Ju and Yijie Wei and Xi Chen and Jie Gu",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185311",

language = "English (US)",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023",

address = "United States",

}

Ju, Y, Wei, Y, Chen, X & Gu, J 2023, A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 6/11/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185311

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. / Ju, Yuhao; Wei, Yijie; Chen, Xi et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

AU - Ju, Yuhao

AU - Wei, Yijie

AU - Chen, Xi

AU - Gu, Jie

PY - 2023

Y1 - 2023

N2 - This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.

AB - This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.

UR - http://www.scopus.com/inward/record.url?scp=85167587401&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85167587401&partnerID=8YFLogxK

U2 - 10.23919/VLSITechnologyandCir57934.2023.10185311

DO - 10.23919/VLSITechnologyandCir57934.2023.10185311

M3 - Conference contribution

AN - SCOPUS:85167587401

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

Y2 - 11 June 2023 through 16 June 2023

ER -

Ju Y, Wei Y, Chen X, Gu J. A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185311

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

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