A gesture classification SoC for rehabilitation with ADC-less mixed-signal feature extraction and training capable neural network classifier

Yijie Wei, Qiankai Cao, Kofi Otseidu, Levi J. Hargrove, Jie Gu

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents a fully integrated gesture and gait classification system-on-chip (SoC) for rehabilitation application. In order to reduce the power consumption and area cost on the analog front end, special analog-to-digital converter (ADC)-less mixed-signal feature extraction (MSFE) circuits were designed to directly generate eight commonly used time-domain features to eliminate the area cost of ADC. A fully connected neural network classifier was implemented supporting: 1) on-chip learning to deliver user-specific training for better classification accuracy; 2) dedicated neural network layer to support gait classification; and 3) multi-chip data communication, which transfers only low-dimensional features from the neural network to minimize the communication bottleneck in a sensor fusion environment. A 12-channel test chip was fabricated in a 65-nm low-power process to demonstrate the proposed techniques. The measurements show an average power of 1μW per channel and a 3-ms computational latency as required by the stringent rehabilitation requirement. In addition, the MSFE circuits achieve 3× saving of area compared with the conventional approach, while the communication bandwidth was reduced by 100× due to the transferring of only low-dimensional feature data from the neural network among multiple chips.

Original languageEnglish (US)
Article number9298917
Pages (from-to)876-886
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume56
Issue number3
DOIs
StatePublished - Mar 2021

Keywords

  • Biomedical devices
  • edge device
  • inter-chip communication
  • mixed-signal feature extraction (MSFE)
  • neural network classifier
  • on-chip training

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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