A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Jonggab Kil; Jie Gu; Chris H. Kim

doi:10.1145/1165573.1165590

A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Jonggab Kil^*, Jie Gu, Chris H. Kim

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.

Original language	English (US)
Title of host publication	ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages	67-72
Number of pages	6
Volume	2006
DOIs	https://doi.org/10.1145/1165573.1165590
State	Published - Dec 1 2006
Event	ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany Duration: Oct 4 2006 → Oct 6 2006

Other

Other	ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
Country/Territory	Germany
City	Tegernsee, Bavaria
Period	10/4/06 → 10/6/06

Keywords

Capacitive boosting
Clock skew
Global interconnect
Sub-threshold circuit
Variation tolerance

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/1165573.1165590

Cite this

@inproceedings{7b35c3905c8f42428c9587cd1251b8ef,

title = "A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting",

abstract = "This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.",

keywords = "Capacitive boosting, Clock skew, Global interconnect, Sub-threshold circuit, Variation tolerance",

author = "Jonggab Kil and Jie Gu and Kim, {Chris H.}",

year = "2006",

month = dec,

day = "1",

doi = "10.1145/1165573.1165590",

language = "English (US)",

isbn = "1595934626",

volume = "2006",

pages = "67--72",

booktitle = "ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design",

note = "ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design ; Conference date: 04-10-2006 Through 06-10-2006",

}

Kil, J, Gu, J & Kim, CH 2006, A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting. in ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. vol. 2006, pp. 67-72, ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design, Tegernsee, Bavaria, Germany, 10/4/06. https://doi.org/10.1145/1165573.1165590

TY - GEN

T1 - A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

AU - Kil, Jonggab

AU - Gu, Jie

AU - Kim, Chris H.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.

AB - This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.

KW - Capacitive boosting

KW - Clock skew

KW - Global interconnect

KW - Sub-threshold circuit

KW - Variation tolerance

UR - http://www.scopus.com/inward/record.url?scp=34247226623&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34247226623&partnerID=8YFLogxK

U2 - 10.1145/1165573.1165590

DO - 10.1145/1165573.1165590

M3 - Conference contribution

AN - SCOPUS:34247226623

SN - 1595934626

SN - 9781595934628

VL - 2006

SP - 67

EP - 72

BT - ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design

T2 - ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design

Y2 - 4 October 2006 through 6 October 2006

ER -

A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Abstract

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this