A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Jonggab Kil*, Jie Gu, Chris H. Kim

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%76% reduction in $3\sigma$ clock skew value and 84%88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-$\mu$m 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6 $\times$ faster switching speed and 2.4$\times$ less delay sensitivity under temperature variations.

Original languageEnglish (US)
Article number4459695
Pages (from-to)456-465
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number4
DOIs
StatePublished - Apr 1 2008

Keywords

  • Capacitive boosting
  • Clock distribution network
  • Global wire delay
  • Subthreshold circuits

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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