A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Engineering

• Electric Potential 100%
• Capacitive 100%
• Networks (Circuits) 100%
• Reduction 100%
• High Speed 100%
• Temperature 100%
• Interconnects 100%
• Measurement 50%
• Gate Voltage 50%
• Temperature Fluctuation 50%
• Clock Skew 50%
• Switching Speed 50%
• Clock Distribution Networks 50%
• Simulation 50%
• Demonstrates 50%
• Performance 50%
• Fits and Tolerances 50%
• Operating Region 50%

INIS

• variations 100%
• speed 100%
• voltage 75%
• reduction 50%
• metals 25%
• comparative evaluations 25%
• simulation 25%
• sensitivity 25%
• performance 25%
• values 25%
• distribution 25%
• tolerance 25%
• wires 25%
• fluctuations 25%
• transistors 25%

Computer Science

• Boosting 100%
• Clock Skew 50%
• Clock Distribution Network 50%
• Threshold Region 50%
• Delay Variation 50%
• Delay Sensitivity 50%
• Simulation 50%