A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

Keyphrases

• Speed Variation 100%
• Subthreshold Circuit 100%
• Variation Tolerance 100%
• Performance Enhancement 50%
• Measurement Results 50%
• In(III) 50%
• Temperature Variation 50%
• Gate Voltage 50%
• Suprathreshold 50%
• Delay-sensitive 50%
• PVT Variations 50%
• Clock Skew 50%
• Driver Transistor 50%
• Delay Variation 50%
• CMOS Process 50%
• Operating Region 50%
• Wire Delay 50%
• Subthreshold Region 50%
• Clock Distribution Network 50%
• Fast Switching Speed 50%
• Less Delay 50%
• Threshold Region 50%

Engineering

• Capacitive 100%
• Interconnects 100%
• Gate Voltage 50%
• Switching Speed 50%
• Clock Distribution Networks 50%
• Fits and Tolerances 50%
• Operating Region 50%