A low power FPGA routing architecture

Somsubhra Mondal*, Seda Ogrenci Memik

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations

Abstract

Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important criterion that needs improvement. In this paper, we propose an interconnect architecture, where voltage scaling is applied within the programmable interconnect structure of the FPGA. We present an evaluation of the overhead associated with dual-V dd-dual-V t interconnect architecture and present results on the impact of this routing architecture on area and delay. Our experiments reveal that an average reduction of 23.45% (as high as 47%) in total interconnect power is achievable with 11.75% worst-case delay penalty and 6% area overhead on average.

Original languageEnglish (US)
Article number1464814
Pages (from-to)1222-1225
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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