A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

Farah Fahim*, Siddhartha Joshi, Seda Ogrenci-Memik, Hooman Mohseni

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a 64×64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of 50 kfps, achieved with a dedicated output for every ( 32×32 ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

Original languageEnglish (US)
Article number8930978
Pages (from-to)576-584
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number2
DOIs
StatePublished - Feb 2020

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Keywords

  • Arbitration tree
  • data sparsification
  • pixel detector readout
  • priority encoder (PE)
  • zero suppression

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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