TY - JOUR
T1 - A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree
AU - Fahim, Farah
AU - Joshi, Siddhartha
AU - Ogrenci-Memik, Seda
AU - Mohseni, Hooman
N1 - Funding Information:
The authors would like to thank Fermilab colleague and Group Leader G. Deptuch for suggesting the improved form of a priority-encoder-based readout controller for use in pixel detectors. They would also like to thank the Fermilab ASIC Design Group Staff and Particle Physics Division Management for supporting this article. They would also like to thank S. Holm, Fermilab, and L. Kadłubowski, AGH-UST Cracow for developing the readout system to test the chip described in this article. This document was prepared by using the resources of the Fermi National Accelerator Laboratory (Fermilab), a U.S. Department of Energy, Office of Science, HEP User Facility. Fermilab is managed by Fermi Research Alliance, LLC (FRA), acting under Contract No. DE-AC02-07CH11359.
Funding Information:
Manuscript received May 15, 2019; revised September 12, 2019; accepted October 8, 2019. Date of publication December 11, 2019; date of current version January 21, 2020. This work was supported by Fermi Research Alliance, LLC through the U.S. Department of Energy, Office of Science, Office of High Energy Physics, under Contract DE-AC02-07CH11359. (Corresponding author: Farah Fahim.) F. Fahim is with the ASIC Development Group of the Electrical Engineering, Department of the Particle Physics Division, Fermi National Accelerator Laboratory, Batavia, IL 60510 USA, and also with the Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL 60208 USA (e-mail: farah@fnal.gov).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a 64×64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of 50 kfps, achieved with a dedicated output for every ( 32×32 ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.
AB - In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a 64×64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of 50 kfps, achieved with a dedicated output for every ( 32×32 ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.
KW - Arbitration tree
KW - data sparsification
KW - pixel detector readout
KW - priority encoder (PE)
KW - zero suppression
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U2 - 10.1109/TVLSI.2019.2953871
DO - 10.1109/TVLSI.2019.2953871
M3 - Article
AN - SCOPUS:85078700878
SN - 1063-8210
VL - 28
SP - 576
EP - 584
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 2
M1 - 8930978
ER -