A methodology for power characterization of associative memories

Dawei Li; Siddhartha Joshi; Seda Ogrenci-Memik; James Hoff; Sergo Jindariani; Tiehui Liu; Jamieson Olsen; Nhan Tran

doi:10.1109/ICCD.2015.7357156

A methodology for power characterization of associative memories

Dawei Li, Siddhartha Joshi, Seda Ogrenci-Memik, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-Time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.

Original language	English (US)
Title of host publication	Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	491-498
Number of pages	8
ISBN (Electronic)	9781467371650
DOIs	https://doi.org/10.1109/ICCD.2015.7357156
State	Published - Dec 14 2015
Event	33rd IEEE International Conference on Computer Design, ICCD 2015 - New York City, United States Duration: Oct 18 2015 → Oct 21 2015

Publication series

Name	Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015

Other

Other	33rd IEEE International Conference on Computer Design, ICCD 2015
Country/Territory	United States
City	New York City
Period	10/18/15 → 10/21/15

Keywords

Content addressable memory (CAM)
NAND cell
NOR cell
Pattern Recognition
Ternary cell
VLSI circuits
digital electronic circuits
power modeling

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications

Access to Document

10.1109/ICCD.2015.7357156

Cite this

Li, D., Joshi, S., Ogrenci-Memik, S., Hoff, J., Jindariani, S., Liu, T., Olsen, J., & Tran, N. (2015). A methodology for power characterization of associative memories. In Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015 (pp. 491-498). [7357156] (Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2015.7357156

Li, Dawei ; Joshi, Siddhartha ; Ogrenci-Memik, Seda et al. / A methodology for power characterization of associative memories. Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 491-498 (Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015).

@inproceedings{3ba5a6e394894d2ca8ed61a9adfcd62d,

title = "A methodology for power characterization of associative memories",

abstract = "Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-Time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.",

keywords = "Content addressable memory (CAM), NAND cell, NOR cell, Pattern Recognition, Ternary cell, VLSI circuits, digital electronic circuits, power modeling",

author = "Dawei Li and Siddhartha Joshi and Seda Ogrenci-Memik and James Hoff and Sergo Jindariani and Tiehui Liu and Jamieson Olsen and Nhan Tran",

note = "Funding Information: Visiting Scholars Program, NSF CCF-1218768, and CCF-1422489 Publisher Copyright: {\textcopyright} 2015 IEEE.; 33rd IEEE International Conference on Computer Design, ICCD 2015 ; Conference date: 18-10-2015 Through 21-10-2015",

year = "2015",

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doi = "10.1109/ICCD.2015.7357156",

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series = "Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015",

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Li, D, Joshi, S, Ogrenci-Memik, S, Hoff, J, Jindariani, S, Liu, T, Olsen, J & Tran, N 2015, A methodology for power characterization of associative memories. in Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015., 7357156, Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015, Institute of Electrical and Electronics Engineers Inc., pp. 491-498, 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, United States, 10/18/15. https://doi.org/10.1109/ICCD.2015.7357156

A methodology for power characterization of associative memories. / Li, Dawei; Joshi, Siddhartha; Ogrenci-Memik, Seda et al.

Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 491-498 7357156 (Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Joshi, Siddhartha

AU - Ogrenci-Memik, Seda

AU - Hoff, James

AU - Jindariani, Sergo

AU - Liu, Tiehui

AU - Olsen, Jamieson

AU - Tran, Nhan

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N2 - Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-Time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.

AB - Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-Time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.

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BT - Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015

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Li D, Joshi S, Ogrenci-Memik S, Hoff J, Jindariani S, Liu T et al. A methodology for power characterization of associative memories. In Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 491-498. 7357156. (Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015). doi: 10.1109/ICCD.2015.7357156

A methodology for power characterization of associative memories

Abstract

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Keywords

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