A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices

Zhengyu Chen; Sihua Fu; Qiankai Cao; Jie Gu

doi:10.1109/VLSICircuits18222.2020.9162829

A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices

Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.

Original language	English (US)
Title of host publication	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728199429
DOIs	https://doi.org/10.1109/VLSICircuits18222.2020.9162829
State	Published - Jun 2020
Event	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States Duration: Jun 16 2020 → Jun 19 2020

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2020-June

Conference

Conference	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Country/Territory	United States
City	Honolulu
Period	6/16/20 → 6/19/20

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSICircuits18222.2020.9162829

Cite this

Chen, Z., Fu, S., Cao, Q., & Gu, J. (2020). A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings [9162829] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSICircuits18222.2020.9162829

Chen, Zhengyu ; Fu, Sihua ; Cao, Qiankai ; Gu, Jie. / A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{848fdc80a80c493dbb560a2fadb9a91d,

title = "A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices",

abstract = "This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.",

author = "Zhengyu Chen and Sihua Fu and Qiankai Cao and Jie Gu",

note = "Funding Information: Fig. 6 Die photo and comparison table. Acknowledgements: This work is supported by NSF (CCF-1846424). References [1] A. Radford, et al., arXiv, 2015. [2] M. Liu, et. al. CICC{\textquoteright}17. [3] N. Cao, et al., ISSCC{\textquoteright}19. [4] A. Sayal, et al., ISSCC{\textquoteright}19. [5] E. H. Lee, et al., ISSCC{\textquoteright}16. [6] Z. Chen, et al., ISSCC{\textquoteright}19. [7] K. Yoshioka, et al., VLSI{\textquoteright}18. [8] FASHION database, https://www.kaggle.com/zalando-research/fashionmnist. [9] EMOJI database, https://getemoji.com/. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 ; Conference date: 16-06-2020 Through 19-06-2020",

year = "2020",

month = jun,

doi = "10.1109/VLSICircuits18222.2020.9162829",

language = "English (US)",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings",

address = "United States",

}

Chen, Z, Fu, S, Cao, Q & Gu, J 2020, A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. in 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings., 9162829, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, United States, 6/16/20. https://doi.org/10.1109/VLSICircuits18222.2020.9162829

A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. / Chen, Zhengyu; Fu, Sihua; Cao, Qiankai; Gu, Jie.

2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9162829 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices

AU - Chen, Zhengyu

AU - Fu, Sihua

AU - Cao, Qiankai

AU - Gu, Jie

N1 - Funding Information: Fig. 6 Die photo and comparison table. Acknowledgements: This work is supported by NSF (CCF-1846424). References [1] A. Radford, et al., arXiv, 2015. [2] M. Liu, et. al. CICC’17. [3] N. Cao, et al., ISSCC’19. [4] A. Sayal, et al., ISSCC’19. [5] E. H. Lee, et al., ISSCC’16. [6] Z. Chen, et al., ISSCC’19. [7] K. Yoshioka, et al., VLSI’18. [8] FASHION database, https://www.kaggle.com/zalando-research/fashionmnist. [9] EMOJI database, https://getemoji.com/. Publisher Copyright: © 2020 IEEE.

PY - 2020/6

Y1 - 2020/6

N2 - This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.

AB - This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.

UR - http://www.scopus.com/inward/record.url?scp=85090186252&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85090186252&partnerID=8YFLogxK

U2 - 10.1109/VLSICircuits18222.2020.9162829

DO - 10.1109/VLSICircuits18222.2020.9162829

M3 - Conference contribution

AN - SCOPUS:85090186252

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020

Y2 - 16 June 2020 through 19 June 2020

ER -

Chen Z, Fu S, Cao Q, Gu J. A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9162829. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSICircuits18222.2020.9162829

A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this