A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices

Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.

Original languageEnglish (US)
Title of host publication2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728199429
DOIs
StatePublished - Jun 2020
Event2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States
Duration: Jun 16 2020Jun 19 2020

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2020-June

Conference

Conference2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
CountryUnited States
CityHonolulu
Period6/16/206/19/20

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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