@inproceedings{848fdc80a80c493dbb560a2fadb9a91d,
title = "A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices",
abstract = "This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.",
author = "Zhengyu Chen and Sihua Fu and Qiankai Cao and Jie Gu",
note = "Funding Information: Fig. 6 Die photo and comparison table. Acknowledgements: This work is supported by NSF (CCF-1846424). References [1] A. Radford, et al., arXiv, 2015. [2] M. Liu, et. al. CICC{\textquoteright}17. [3] N. Cao, et al., ISSCC{\textquoteright}19. [4] A. Sayal, et al., ISSCC{\textquoteright}19. [5] E. H. Lee, et al., ISSCC{\textquoteright}16. [6] Z. Chen, et al., ISSCC{\textquoteright}19. [7] K. Yoshioka, et al., VLSI{\textquoteright}18. [8] FASHION database, https://www.kaggle.com/zalando-research/fashionmnist. [9] EMOJI database, https://getemoji.com/. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 ; Conference date: 16-06-2020 Through 19-06-2020",
year = "2020",
month = jun,
doi = "10.1109/VLSICircuits18222.2020.9162829",
language = "English (US)",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings",
address = "United States",
}