TY - GEN
T1 - A novel N-retry transactional memory model for multi-thread programming
AU - Lu, Kun
AU - Yan, Changhao
AU - Zhou, Hai
AU - Zhou, Dian
AU - Zeng, Xuan
N1 - Funding Information:
This research is supported partly by the National Key Research and Development Program of China (2016YFB0201304), partly by National Natural Science Foundation of China (NSFC) research project under grants 61376040, 61674042, 61574046, 61574044 and 61628402, partly by the Recruitment Program of Global Experts (the Thousand Talents Plan), partly by NSF under CNS-1441695, CCF-1533656, CNS-1651695.
Publisher Copyright:
© 2017 IEEE.
PY - 2018/5/25
Y1 - 2018/5/25
N2 - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.
AB - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.
KW - Intel Transactional Synchronization Extensions-(TSX)
KW - Multi thread programming
KW - Transaction memory
KW - Transactional locking-2
UR - http://www.scopus.com/inward/record.url?scp=85048360616&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048360616&partnerID=8YFLogxK
U2 - 10.1109/ISPA/IUCC.2017.00124
DO - 10.1109/ISPA/IUCC.2017.00124
M3 - Conference contribution
AN - SCOPUS:85048360616
T3 - Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
SP - 814
EP - 821
BT - Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
A2 - Martinez, Gregorio
A2 - Hill, Richard
A2 - Fox, Geoffrey
A2 - Mueller, Peter
A2 - Wang, Guojun
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
Y2 - 12 December 2017 through 15 December 2017
ER -