A novel N-retry transactional memory model for multi-thread programming

Kun Lu, Changhao Yan*, Hai Zhou, Dian Zhou, Xuan Zeng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

Original languageEnglish (US)
Title of host publicationProceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
EditorsGregorio Martinez, Richard Hill, Geoffrey Fox, Peter Mueller, Guojun Wang
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages814-821
Number of pages8
ISBN (Electronic)9781538637906
DOIs
StatePublished - May 25 2018
Event15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 - Guangzhou, China
Duration: Dec 12 2017Dec 15 2017

Publication series

NameProceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

Other

Other15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
CountryChina
CityGuangzhou
Period12/12/1712/15/17

Fingerprint

Multi-thread
Transactional Memory
Memory Model
Computer programming
Transactions
Programming
Data storage equipment
Computer hardware
Parallel programming
Paradigm
Hardware
Synchronization
Durability
Software
Parallel Programming

Keywords

  • Intel Transactional Synchronization Extensions-(TSX)
  • Multi thread programming
  • Transaction memory
  • Transactional locking-2

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Information Systems
  • Control and Optimization
  • Computer Networks and Communications

Cite this

Lu, K., Yan, C., Zhou, H., Zhou, D., & Zeng, X. (2018). A novel N-retry transactional memory model for multi-thread programming. In G. Martinez, R. Hill, G. Fox, P. Mueller, & G. Wang (Eds.), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 (pp. 814-821). (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPA/IUCC.2017.00124
Lu, Kun ; Yan, Changhao ; Zhou, Hai ; Zhou, Dian ; Zeng, Xuan. / A novel N-retry transactional memory model for multi-thread programming. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. editor / Gregorio Martinez ; Richard Hill ; Geoffrey Fox ; Peter Mueller ; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 814-821 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).
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abstract = "Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40{\%} of transaction aborts, and improve the parallel performance 25{\%} on software TM platform and 11{\%} on hardware TM platform.",
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author = "Kun Lu and Changhao Yan and Hai Zhou and Dian Zhou and Xuan Zeng",
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Lu, K, Yan, C, Zhou, H, Zhou, D & Zeng, X 2018, A novel N-retry transactional memory model for multi-thread programming. in G Martinez, R Hill, G Fox, P Mueller & G Wang (eds), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 814-821, 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Guangzhou, China, 12/12/17. https://doi.org/10.1109/ISPA/IUCC.2017.00124

A novel N-retry transactional memory model for multi-thread programming. / Lu, Kun; Yan, Changhao; Zhou, Hai; Zhou, Dian; Zeng, Xuan.

Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. ed. / Gregorio Martinez; Richard Hill; Geoffrey Fox; Peter Mueller; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. p. 814-821 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A novel N-retry transactional memory model for multi-thread programming

AU - Lu, Kun

AU - Yan, Changhao

AU - Zhou, Hai

AU - Zhou, Dian

AU - Zeng, Xuan

PY - 2018/5/25

Y1 - 2018/5/25

N2 - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

AB - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

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KW - Transactional locking-2

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M3 - Conference contribution

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A2 - Wang, Guojun

PB - Institute of Electrical and Electronics Engineers Inc.

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Lu K, Yan C, Zhou H, Zhou D, Zeng X. A novel N-retry transactional memory model for multi-thread programming. In Martinez G, Hill R, Fox G, Mueller P, Wang G, editors, Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 814-821. (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). https://doi.org/10.1109/ISPA/IUCC.2017.00124