A novel N-retry transactional memory model for multi-thread programming

Kun Lu; Changhao Yan; Hai Zhou; Dian Zhou; Xuan Zeng

doi:10.1109/ISPA/IUCC.2017.00124

A novel N-retry transactional memory model for multi-thread programming

Kun Lu, Changhao Yan^*, Hai Zhou, Dian Zhou, Xuan Zeng

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

Original language	English (US)
Title of host publication	Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
Editors	Gregorio Martinez, Richard Hill, Geoffrey Fox, Peter Mueller, Guojun Wang
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	814-821
Number of pages	8
ISBN (Electronic)	9781538637906
DOIs	https://doi.org/10.1109/ISPA/IUCC.2017.00124
State	Published - May 25 2018
Event	15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 - Guangzhou, China Duration: Dec 12 2017 → Dec 15 2017

Publication series

Name	Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

Other

Other	15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
Country/Territory	China
City	Guangzhou
Period	12/12/17 → 12/15/17

Funding

This research is supported partly by the National Key Research and Development Program of China (2016YFB0201304), partly by National Natural Science Foundation of China (NSFC) research project under grants 61376040, 61674042, 61574046, 61574044 and 61628402, partly by the Recruitment Program of Global Experts (the Thousand Talents Plan), partly by NSF under CNS-1441695, CCF-1533656, CNS-1651695.

Keywords

Intel Transactional Synchronization Extensions-(TSX)
Multi thread programming
Transaction memory
Transactional locking-2

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture
Information Systems
Control and Optimization
Computer Networks and Communications

Access to Document

10.1109/ISPA/IUCC.2017.00124

Cite this

Lu, K., Yan, C., Zhou, H., Zhou, D., & Zeng, X. (2018). A novel N-retry transactional memory model for multi-thread programming. In G. Martinez, R. Hill, G. Fox, P. Mueller, & G. Wang (Eds.), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 (pp. 814-821). (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPA/IUCC.2017.00124

Lu, Kun ; Yan, Changhao ; Zhou, Hai et al. / A novel N-retry transactional memory model for multi-thread programming. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. editor / Gregorio Martinez ; Richard Hill ; Geoffrey Fox ; Peter Mueller ; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 814-821 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

@inproceedings{73886f4b87794270aa8b9fbcfef9b3d9,

title = "A novel N-retry transactional memory model for multi-thread programming",

abstract = "Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40\% of transaction aborts, and improve the parallel performance 25\% on software TM platform and 11\% on hardware TM platform.",

keywords = "Intel Transactional Synchronization Extensions-(TSX), Multi thread programming, Transaction memory, Transactional locking-2",

author = "Kun Lu and Changhao Yan and Hai Zhou and Dian Zhou and Xuan Zeng",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 ; Conference date: 12-12-2017 Through 15-12-2017",

year = "2018",

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editor = "Gregorio Martinez and Richard Hill and Geoffrey Fox and Peter Mueller and Guojun Wang",

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Lu, K, Yan, C, Zhou, H, Zhou, D & Zeng, X 2018, A novel N-retry transactional memory model for multi-thread programming. in G Martinez, R Hill, G Fox, P Mueller & G Wang (eds), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 814-821, 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Guangzhou, China, 12/12/17. https://doi.org/10.1109/ISPA/IUCC.2017.00124

A novel N-retry transactional memory model for multi-thread programming. / Lu, Kun; Yan, Changhao; Zhou, Hai et al.
Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. ed. / Gregorio Martinez; Richard Hill; Geoffrey Fox; Peter Mueller; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. p. 814-821 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A novel N-retry transactional memory model for multi-thread programming

AU - Lu, Kun

AU - Yan, Changhao

AU - Zhou, Hai

AU - Zhou, Dian

AU - Zeng, Xuan

PY - 2018/5/25

Y1 - 2018/5/25

N2 - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

AB - Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel pro-gramming paradigm. Transaction memory maintains Atomic-ity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-Thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

KW - Intel Transactional Synchronization Extensions-(TSX)

KW - Multi thread programming

KW - Transaction memory

KW - Transactional locking-2

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Lu K, Yan C, Zhou H, Zhou D, Zeng X. A novel N-retry transactional memory model for multi-thread programming. In Martinez G, Hill R, Fox G, Mueller P, Wang G, editors, Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 814-821. (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). doi: 10.1109/ISPA/IUCC.2017.00124

A novel N-retry transactional memory model for multi-thread programming

Abstract

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Keywords

ASJC Scopus subject areas

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