Abstract
We preform device simulations of a tin sulfide (SnS) device stack using SCAPS to define a path to 10% efficient devices. We determine and constrain a baseline device model using recent experimental results on one of our 3.9% efficient cells. Through a multistep fitting process, we find a conduction band cliff of -0.2 eV between SnS and Zn(O,S) to be limiting the open circuit voltage (VOC). To move towards a higher efficiency, we can optimize the buffer layer band alignment. Improvement of the SnS lifetime to >1 ns is necessary to reach 10% efficiency. Additionally, absorber-buffer interface recombination must be suppressed, either by reducing recombination activity of defects or creating a strong inversion layer at the interface.
Original language | English (US) |
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Title of host publication | 2014 IEEE 40th Photovoltaic Specialist Conference, PVSC 2014 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 2373-2378 |
Number of pages | 6 |
ISBN (Electronic) | 9781479943982 |
DOIs | |
State | Published - Oct 15 2014 |
Event | 40th IEEE Photovoltaic Specialist Conference, PVSC 2014 - Denver, United States Duration: Jun 8 2014 → Jun 13 2014 |
Other
Other | 40th IEEE Photovoltaic Specialist Conference, PVSC 2014 |
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Country/Territory | United States |
City | Denver |
Period | 6/8/14 → 6/13/14 |
Keywords
- chalcogenide solar cells
- device simulation
- paths toward higher efficiency
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials