A reconfigurable and hierarchical parallel processing architecture: Performance results for stereo vision

Alok N. Choudhary*, Subhodev Das, Narendra Ahuja, Janak H. Patel

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

A multiprocessor architecture called NETRA is discussed. It is highly reconfigurable and does not involve the use of complex interconnection schemes. The topology of this multiprocessor is recursively defined and is therefore easily scalable from small to large systems. It has a tree-type hierarchical architecture featuring leaf nodes that consist of a cluster of small but powerful processors connected via a programmable crossbar with selective broadcast capability. The architecture is simulated on a hypercube multiprocessors and the performance of one processor cluster is evaluated for stereo-vision tasks. The particular stereo algorithm selected for implementation requires computation of the two-dimensional fast Fourier transform (2-D FFT), template matching, histogram computation, and least-squares surface fitting. Static partitioning of data is used for the data-independent tasks such as 2-D FFT and dynamic scheduling, and load balancing is used for the data-dependent tasks of feature matching and disambiguation. The superior performance of the architecture is demonstrated by comparing the results with that of a similar implementation on the hypercube itself.

Original languageEnglish (US)
Pages (from-to)389-393
Number of pages5
JournalProceedings - International Conference on Pattern Recognition
Volume2
StatePublished - Dec 1 1990

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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